James Di Sarro

Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations

Souvick Mitra, Junjun Li, Robert Gauthier, 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

Influence of package parasitic elements on CDM stress

Robert Gauthier, James Di Sarro, Bill Reynold, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network

Junjun Li, Robert Gauthier, Shunhua Chang, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology

Souvick Mitra, Robert Gauthier, Elyse Rosenbaum, 2009, 2009 31st EOS/ESD Symposium.

Characterization of high-k/metal gate stack breakdown in the time scale of ESD events

Souvick Mitra, Yang Yang, Dimitris E. Ioannou, 2010, 2010 IEEE International Reliability Physics Symposium.

Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions

Robert Gauthier, James Di Sarro, Junjun Li, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.