R. Morusupalli

On the Mechanical Stresses of Cu Through-Silicon Via (TSV) Samples Fabricated by SK Hynix vs. SEMATECH – Enabling Robust and Reliable 3-D Interconnect/Integrated Circuit (IC) Technology

M. Kunz, N. Tamura, Kwang-yoo Byun, 2016 .

Comparison of Line stress predictions with measured electromigration failure times

J. R. Patel, W. Nix, R. Morusupalli, 2007, 2007 IEEE International Integrated Reliability Workshop Final Report.