Nereo Markulic

发表

3.6 A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with −41.3 DB EVM at 1024 OAM in 28NM CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2018, 2018 IEEE Symposium on VLSI Circuits.

Conclusion and Future Outlook

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2019 .

A Background-Calibrated Digital Subsampling Polar Transmitter

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2019 .

A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm

Jan Craninckx, Ewout Martens, Nereo Markulic, 2020, 2020 IEEE Symposium on VLSI Circuits.

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications

Kathleen Philips, Christian Bachmann, Yao-Hong Liu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

26.1 A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error

Jan Craninckx, Nereo Markulic, Qixian Shi, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth

Jan Craninckx, Nereo Markulic, Qixian Shi, 2019, IEEE Journal of Solid-State Circuits.

A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With −41.3-dB EVM at 1024 QAM in 28-nm CMOS

Jan Craninckx, Piet Wambacq, Ewout Martens, 2019, IEEE Journal of Solid-State Circuits.

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, IEEE Journal of Solid-State Circuits.

DTC-based subsampling PLLs for low-noise synthesis and two-point modulation

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2020 .

9.7 a self-calibrated 10mb/s phase modulator with -37.4db evm based on a 10.1-to-12.4ghz, -246.6db-fom, fractional-n subsampling pll

Jan Craninckx, Piet Wambacq, Ewout Martens, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2020, IEEE Journal of Solid-State Circuits.

3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A Fractional-n subsampling PLL based on a digital-to-time converter

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2016, 2016 39th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis

Jan Craninckx, Piet Wambacq, Kuba Raczkowski, 2019 .

A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

Jan Craninckx, Benjamin P. Hershberg, Kuba Raczkowski, 2015, IEEE Journal of Solid-State Circuits.

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Jan Craninckx, Piet Wambacq, Nereo Markulic, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC

Rui Paulo Martins, Jan Craninckx, Chi-Hang Chan, 2021, 2021 Symposium on VLSI Circuits.

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS

Jan Craninckx, Ewout Martens, Benjamin P. Hershberg, 2021, 2021 Symposium on VLSI Circuits.