D. Casarotto

A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

Scott Halle, Jack A. Mandelman, Carl J. Radens, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

A high-speed 128-kb MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2004, IEEE Journal of Solid-State Circuits.

A high-speed 128 Kbit MRAM core for future universal memory applications

H. Hoenigschmid, D. Casarotto, G. Muller, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

J. Benedict, T. Kirihata, C. Norris, 2006, 2006 International Electron Devices Meeting.

A 0.135 pm2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/l6Gb DRAM

Scott J. Bukofsky, Scott Halle, Jack A. Mandelman, 2000 .

An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

S. Kudelka, N. Arnold, U. Gruening, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

U. Gruening, D. Casarotto, J. Alsmeier, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).