Chien-Mo James Li

发表

Placement Optimization of Flexible TFT Digital Circuits

Chester Liu, En-Hua Ma, Wen-En Wei, 2011, IEEE Design & Test of Computers.

Robust test pattern generation for hold-time faults in nanometer technologies

Chien-Mo James Li, Yu-Hao Ho, Yo-Wei Chen, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis

Chien-Mo James Li, Wei-Lin Tsai, Wei-Chih Liu, 2012, IEEE Transactions on Computers.

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction

Jie-Hong Roland Jiang, Yao-Wen Chang, Chien-Mo James Li, 2018, DAC.

Diagnosis of sequence-dependent chips

Edward J. McCluskey, Chien-Mo James Li, E. McCluskey, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies

Chien-Mo James Li, Chun-Yi Lee, Hung-Mao Lin, 2007, 2007 Asia and South Pacific Design Automation Conference.

Jump scan: a DFT technique for low power testing

Chien-Mo James Li, Min-Hao Chiu, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

qATG: Automatic Test Generation for Quantum Circuits

Chien-Mo James Li, Chen-Hung Wu, Cheng-Yun Hsieh, 2020, 2020 IEEE International Test Conference (ITC).

Survey of Scan Chain Diagnosis

Wu-Tung Cheng, Chien-Mo James Li, Ruifeng Guo, 2008, IEEE Design & Test of Computers.

Physical-aware systematic multiple defect diagnosis

Chien-Mo James Li, Jih-Nung Lee, Chun-Yi Kuo, 2014, IET Comput. Digit. Tech..

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

Chien-Mo James Li, Hung-Mao Lin, Fang-Min Wang, 2007, IEEE Transactions on Computers.

Machine-learning-based Dynamic IR Drop Prediction for ECO

Chien-Mo James Li, Yen-Chun Fang, Heng-Yi Lin, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Chien-Mo James Li, Geng-Ming Chiu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs

Michael S. Hsiao, Shianling Wu, Xiaoqing Wen, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

3D IC test scheduling using simulated annealing

Krishnendu Chakrabarty, Chien-Mo James Li, Chun-Yi Kuo, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits

Chien-Mo James Li, I-Chun Cheng, Shiue-Tsung Shen, 2009, 2009 Asian Test Symposium.

An at-speed self-testable technique for the high speed domino adder

Charlie Chung-Ping Chen, Chien-Mo James Li, Chi-Wei Liu, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

CSER: BISER-based concurrent soft-error resilience

Nur A. Touba, Shianling Wu, Chien-Mo James Li, 2010, 2010 28th VLSI Test Symposium (VTS).

Test Generation of Path Delay Faults Induced by Defects in Power TSV

Krishnendu Chakrabarty, Tzong-Lin Wu, Yi-Chang Lu, 2013, 2013 22nd Asian Test Symposium.

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Krishnendu Chakrabarty, Yi-Chang Lu, Chien-Mo James Li, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Time-space test response compaction and diagnosis based on BCH codes

Chien-Mo James Li, W.-C. Wang, F.-M. Wang, 2009, IET Comput. Digit. Tech..

Diagnosis technique for Clustered Multiple Transition Delay Faults

Chien-Mo James Li, Po-Wei Chen, Yan-Shen You, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

A new method for parameter estimation of high-order polynomial-phase signals

Chien-Mo James Li, Lei Zuo, Zeyu Wang, 2018, Signal Process..

Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips

Chien-Mo James Li, A. Rao, C.-Y. Hsu, 2011, IET Comput. Digit. Tech..

ATPG and Test Compression for Probabilistic Circuits

Chien-Mo James Li, Kai-Chieh Yang, Chen-Hung Wu, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk

Chien-Mo James Li, Hung-Yi Hsieh, Ming-Hong Tsai, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects

Chien-Mo James Li, Po-Juei Chen, Charles C. C. Liu, 2011, 2011 Asian Test Symposium.

Test methodology for dual-rail asynchronous circuits

Chien-Mo James Li, Ting-Yu Shen, Kuan-Yen Huang, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing

Chien-Mo James Li, Chun-Yi Lee, 2007, J. Low Power Electron..

High Efficiency and Low Overkill Testing for Probabilistic Circuits

Chien-Mo James Li, Chen-Hung Wu, Cheng-Yun Hsieh, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example

Charlie Chung-Ping Chen, Chien-Mo James Li, Min-Han Hsieh, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Divide and conquer diagnosis for multiple defects

Ying-Yen Chen, Chien-Mo James Li, Po-Hao Chen, 2014, 2014 International Test Conference.

A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse

Chien-Mo James Li, Hung-I Lee, Chen-Yo Han, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing for tunneling opens

Edward J. McCluskey, Chien-Mo James Li, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Diagnosis of single stuck-at faults and multiple timing faults in scan chains

Chien-Mo James Li, C. Li, 2005, IEEE Trans. Very Large Scale Integr. Syst..

GPU-based timing-aware test generation for small delay defects

Michael S. Hsiao, Chien-Mo James Li, Laung-Terng Wang, 2014, 2014 19th IEEE European Test Symposium (ETS).

Simultaneous capture and shift power reduction test pattern generator for scan testing

Chien-Mo James Li, H.-T. Lin, 2008, IET Comput. Digit. Tech..

Effective and Economic Phase Noise Testing for Single-Chip TV Tuners

Chien-Mo James Li, Po-Chou Lin, Chih-Ming Chiang, 2008, IEEE Transactions on Instrumentation and Measurement.

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

Chien-Mo James Li, Yu-Ching Li, Cheng-Yu Han, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Parallel order ATPG for test compaction

Chien-Mo James Li, Yu-Hao Ho, Chih-Ming Chang, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Diagnosis of tunneling opens

Edward J. McCluskey, Chien-Mo James Li, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Test clock domain optimization for peak power supply noise reduction during scan

Chien-Mo James Li, Jen-Yang Wen, Yu-Chuan Huang, 2011, 2011 IEEE International Test Conference.

Test Pattern Compression for Probabilistic Circuits

Kai-Jie Yang, Chien-Mo James Li, Chih-Ming Chang, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM

Chen-An Chen, Chien-Mo James Li, Liang-Chia Cheng, 2013, 2013 22nd Asian Test Symposium.

PSN-aware circuit test timing prediction using machine learning

Chien-Mo James Li, Yu-Cheng Liu, Cheng-Yu Han, 2017, IET Comput. Digit. Tech..

Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns

Chien-Mo James Li, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

ELF-Murphy data on defects and tests sets

Ahmad A. Al-Yamani, Edward J. McCluskey, Chien-Mo James Li, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

Edward J. McCluskey, Chien-Mo James Li, Jonathan T.-Y. Chang, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

Diagnosis of Logic-to-chain Bridging Faults

Chien-Mo James Li, Wei-Lin Tsai, Wei-Chih Liu, 2008, 2008 IEEE International Test Conference.

Diagnosis of Multiple Scan Chain Timing Faults

Chien-Mo James Li, Wei-Chih Liu, Wei-Shun Chuang, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits

Chien-Mo James Li, Chen-Hung Wu, Cheng-Yun Hsieh, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Test Pattern Modification for Average IR-Drop Reduction

Xiaoqing Wen, Chien-Mo James Li, Hung-Yi Hsieh, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects

Chien-Mo James Li, Ang-Feng Lin, Kuan-Yu Liao, 2015, VLSI Design, Automation and Test(VLSI-DAT).

An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

Chien-Mo James Li, Chi-Hsuan Cheng, C. Li, 2011, J. Electron. Test..

Testing for resistive opens and stuck opens

Edward J. McCluskey, Chien-Mo James Li, Chao-Wen Tseng, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Physical-aware diagnosis of multiple interconnect defects

Chien-Mo James Li, Po-Wei Chen, Po-Hao Chen, 2017, 2017 International Test Conference in Asia (ITC-Asia).

Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

Edward J. McCluskey, Chien-Mo James Li, E. McCluskey, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Power scan: DFT for power switches in VLSI designs

Chien-Mo James Li, Bing-Chuan Bai, Augusli Kifli, 2009, 2009 International Test Conference.

Compact Test Pattern Selection for Small Delay Defect

Chien-Mo James Li, Jiann-Chyi Rau, Chia-Yuan Chang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains

Chien-Mo James Li, Hung-Mao Lin, 2005, IEEE International Conference on Test, 2005..

Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations

Chien-Mo James Li, Yu-Ching Li, Heng-Yi Lin, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Static timing analysis for flexible TFT circuits

Chester Liu, En-Hua Ma, Chien-Mo James Li, 2010, Design Automation Conference.

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

Chien-Mo James Li, Yu-Hao Ho, Yo-Wei Chen, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

BIST design optimization for large-scale embedded memory cores

Yao-Wen Chang, Chien-Mo James Li, Ming-Tung Chang, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Fault modeling and testing of retention flip-flops in low power designs

Chien-Mo James Li, Bing-Chuan Bai, Augusli Kifli, 2009, 2009 Asia and South Pacific Design Automation Conference.

DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

Vasco M. Manquinho, Chien-Mo James Li, Wei-Chung Kao, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics

Chien-Nan Jimmy Liu, Chien-Mo James Li, Yen-Lung Chen, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits

En-Hua Ma, Chien-Mo James Li, Shiue-Tsung Shen, 2009, Asian Test Symposium.

Diagnosis of multiple hold-time and setup-time faults in scan chains

Chien-Mo James Li, 2005, IEEE Transactions on Computers.

IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores

Chien-Mo James Li, Geng-Ming Chiu, 2008, 2008 IEEE International Test Conference.

A Two-level Simultaneous Test Data and Time Reduction Technique for SOC

Chien-Mo James Li, Bing-Chuan Bai, Yu-Te Liaw, 2008, J. Inf. Sci. Eng..

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects

Chien-Mo James Li, Po-Juei Chen, Hsing Jasmine Chao, 2009, 2009 Asian Test Symposium.

Automatic test pattern generation for delay defects using timed characteristic functions

Jie-Hong Roland Jiang, Chien-Mo James Li, Ko-Lung Yuan, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Yu Hu, Yu Zhang, Michael S. Hsiao, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Michael S. Hsiao, Fangfang Li, Wen-Ben Jone, 2012, TODE.

A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

Chien-Mo James Li, Chia-Yuan Chang, Kuan-Yu Liao, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test methodology for PCHB/PCFB Asynchronous Circuits

Chien-Mo James Li, Chia-Cheng Pai, Ting-Yu Shen, 2018, 2018 IEEE International Test Conference (ITC).

GPU-based N-detect transition fault ATPG

Chien-Mo James Li, Kuan-Yu Liao, Sheng-Chang Hsu, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis

Chien-Mo James Li, Wei-Shun Chuang, Yu-Long Kao, 2006, 2006 IEEE International Test Conference.