Chih-Yuan Lu

发表

Manufacturing integrated circuits with FETs.

Kuo-Hua Lee, Chih-Yuan Lu, David Stanley Yaney, 1988 .

Reduction of wafer arcing during high aspect ratio etching

Chih-Yuan Lu, Zusing Yang, Min-Feng Hung, 2017, ASMC 2017.

Intensity weighed focus drilling exposure for maximizing process window of sub-100-nm contact by simulation

Chih-Yuan Lu, Kuang-Chao Chen, Sunwook Jung, 2007, SPIE Advanced Lithography.

Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories

Hsin-Yi Lin, Chih-Yuan Lu, Nian-Jia Wang, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

A novel decomposition of source kernel for OPC modeling

Chih-Yuan Lu, C. T. Hsuan, T. S. Wu, 2010, Advanced Lithography.

Non-Volatile Memory Technology-Today and Tomorrow

Chih-Yuan Lu, Rich Liu, Tao-Cheng Lu, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Optics selection by high magnification optical micrograph in bright field inspection

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2012, 2012 e-Manufacturing & Design Collaboration Symposium (eMDC).

Novel lithography rule check for full-chip side lobe detection

Chih-Yuan Lu, K. C. Chen, T. S. Wu, 2008, SPIE Advanced Lithography.

Quasi-blind voltage contrast in e beam inspection

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2013, 2013 e-Manufacturing & Design Collaboration Symposium (eMDC).

Process solutions for reducing PR residue over non-planar wafer

Chih-Yuan Lu, Elvis Yang, K. C. Chen, 2011, Advanced Lithography.

A Novel P-Poly Gate PNOS Device Featuring High 2nd-Bit Operation Window for Multi-bit/cell Flash Memory Applications

Chih-Yuan Lu, R. Liu, Jau-Yi Wu, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Chih-Yuan Lu, Hang-Ting Lue, Wei-Chen Chen, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface

Chih-Yuan Lu, Nan-Tzu Lian, Tahone Yang, 2010, 2010 IEEE International Reliability Physics Symposium.

FOUP N2 purge engineering in Fab

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2013, 2013 e-Manufacturing & Design Collaboration Symposium (eMDC).

A novel low-voltage hot-carrier (LVHC) programming method for scaled NAND flash cell

Chih-Yuan Lu, J.S. Huang, C.H. Cheng, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Reduction of nuisance rate in inspection using review/inspector cycle optimization methodology

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2011, 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM).

Multiple-step process window aware OPC for hyper-NA lithography

Chih-Yuan Lu, C. T. Hsuan, Fred Lo, 2013, Advanced Lithography.

Reliability investigations of down-stream copper interconnect with different Tungsten-VIA structures

Chih-Yuan Lu, Ming-Yi Lee, R. Chen, 2012, 2012 IEEE International Integrated Reliability Workshop Final Report.

Inspection Flow of Yield Impacting Systematic Defects - Chimin Chen

Chih-Yuan Lu, Rong Lv, Donghua Liu, 2013 .

Performance Impacts of Analog ReRAM Non-ideality on Neuromorphic Computing

Chih-Yuan Lu, Yu-Yu Lin, Chao-Hung Wang, 2019, IEEE Transactions on Electron Devices.

Reliability of barrier engineered charge trapping devices for sub-30nm NAND flash

Chih-Yuan Lu, R. Liu, Hang-Ting Lue, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A Vertical 2T NOR (V2T) Architecture to Enable Scaling and Low-Power Solutions for NOR Flash Technology

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2020, 2020 IEEE Symposium on VLSI Technology.

Tiny physical defects inspection by optimized EBI methodology

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2014, 2014 e-Manufacturing & Design Collaboration Symposium (eMDC).

Novel process window and product yield improvement by eliminating contact shorts

Chih-Yuan Lu, Hong-Ji Lee, Nan-Tzu Lian, 2014, 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).

Performance Enhancement of 3-D NAND Flash Featuring a Two-Step Dummy Wordline Program Waveform and Pair-Bitline Program Scheme

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2020, IEEE Transactions on Electron Devices.

A self-aligned double patterning technology using TiN as the sidewall spacer

Chih-Yuan Lu, Hong-Ji Lee, Nan-Tzu Lian, 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

Use of random telegraph signal as internal probe to study program/erase charge lateral spread in a SONOS flash memory

Chih-Yuan Lu, Tahui Wang, K.C. Chen, 2010, 2010 IEEE International Reliability Physics Symposium.

A novel tite buffered Cu-GeSbTe/SiO2 electrochemical resistive memory (ReRAM)

Chih-Yuan Lu, Kuang-Yeu Hsieh, Yi-Chou Chen, 2010, 2010 Symposium on VLSI Technology.

Reduction of shorts between word lines on charge-trapping flash cell in a self-aligned double patterning technology

Chih-Yuan Lu, Hong-Ji Lee, Nan-Tzu Lian, 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Advantage of Extremely-thin Body (Tsi~3nm) Device to Boost the Memory Window for 3D NAND Flash

Chih-Yuan Lu, W. C. Chen, Hang-Ting Lue, 2019, 2019 Symposium on VLSI Technology.

Modeling and scaling evaluation of junction-free charge-trapping NAND flash devices

Chih-Yuan Lu, Rich Liu, Yi-Hsuan Hsiao, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper)

Chih-Yuan Lu, Hang-Ting Lue, Po-Kai Hsu, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Novel ATHENA mark design to enhance alignment quality in double patterning with spacer process

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2010, Advanced Lithography.

Study of hot-electron assisted programming for split-page 3D vertical gate (VG) NAND flash

Chih-Yuan Lu, Kuo-Pin Chang, Yi-Hsuan Hsiao, 2013, 2013 5th IEEE International Memory Workshop.

3D stackable vertical-gate BE-SONOS NAND flash with layer-aware program-and-read schemes and wave-propagation fail-bit-detection against cross-layer process variations

Meng-Fan Chang, Chih-Yuan Lu, Hang-Ting Lue, 2013, 2013 Symposium on VLSI Circuits.

Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution

Chih-Yuan Lu, Hang-Ting Lue, Wei-Chen Chen, 2020, IEEE International Reliability Physics Symposium.

PEB to development delay influence on contact patterning by negative tone development process

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2013, Advanced Lithography.

A Novel Gate-Sensing and Channel-Sensing Transient Analysis Method for Real-Time Monitoring of Charge Vertical Location in Sonos-Type Devices and its Applications in Reliability Studies

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Adaptive OPC approach based on pattern grouping algorithm

Chih-Yuan Lu, C. T. Hsuan, Fred Lo, 2014, Advanced Lithography.

A comprehensive comparison between double patterning and double patterning with spacer on sub-50nm product implementation

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2008, SPIE Advanced Lithography.

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

Chih-Yuan Lu, Kuang-Chao Chen, Jeng Gong, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Study of Self-Healing 3D NAND Flash with Micro Heater to Improve the Performances and Lifetime for Fast NAND in NVDIMM Applications

Chih-Yuan Lu, Hung-Sheng Chang, Roger Lo, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

Analysis of pattern density on process proximity compensation

Chih-Yuan Lu, Sunwook Jung, Fred Lo, 2007, SPIE Advanced Lithography.

A method for fabricating integrated circuits having FET.

Kuo-Hua Lee, Chih-Yuan Lu, David Stanley Yaney, 1988 .

Read Disturb Evaluations of 3D NAND Flash for Highly Read-Intensive Edge-Computing Inference Device for Artificial Intelligence Applications

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2019, 2019 IEEE 11th International Memory Workshop (IMW).

A highly punchthrough-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell

Chih-Yuan Lu, J.S. Huang, C.H. Cheng, 2008, 2008 IEEE International Electron Devices Meeting.

A study of barrier engineered Al2O3 and HfO2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness

Chih-Yuan Lu, Yung-Tai Hung, Hang-Ting Lue, 2010, 2010 IEEE International Memory Workshop.

Novel hybrid 3D NAND flash memory containing vertical-gate and gate-all-around structures

Chih-Yuan Lu, Zusing Yang, Hong-Ji Lee, 2016, 2016 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash

Chih-Yuan Lu, Kuo-Pin Chang, Yi-Hsuan Hsiao, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Evaluations for a highly scalable, reliable vertical channel SONOS memory

Chih-Yuan Lu, Y. J. Chen, W. P. Lu, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application

Yao-Wen Chang, Chih-Yuan Lu, Kuang-Chao Chen, 2011, 2011 International Reliability Physics Symposium.

Reliability and device scaling challenges of trapping charge flash memories

Chih-Yuan Lu, Tahui Wang, T.C. Lu, 2004, Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743).

A method of setting a memory device of a memory cell

Chih-Yuan Lu, Yi-Chou Chen, 2003 .

Advanced floating gate CD uniformity control in the 75nm node NOR flash memory

Chih-Yuan Lu, Sheng-Yuan Chang, Hong-Ji Lee, 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Metal grain suppression and DOI capture rate improvement in 32 nm technology node

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2011, 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM).

Advanced SPICE modeling for program inhibit operation in NAND flash memories

Chih-Yuan Lu, T. C. Lu, K. C. Chen, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Theoretical Analysis of Planar Flat Floating Gate NAND Flash Device and Experimental Study of Floating-Gate (FG) / Charge-Trapping (CT) Fusion Device for Comprehensive Understanding of Charge Storage and Operation Principle

Chih-Yuan Lu, Roger Lo, Hang-Ting Lue, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

A temperature accelerated model for high state retention loss of nitride storage flash memory

Chih-Yuan Lu, W.J. Tsai, A. Kuo, 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

A novel double-density single-gate vertical-channel (SGVC) 3D NAND flash featuring a flat-channel device with excellent layer uniformity

Chih-Yuan Lu, Hang-Ting Lue, Chia-Jung Chiu, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Chip-level reliability study of barrier engineered (BE) floating gate (FG) Flash memory devices

Chih-Yuan Lu, T. Yang, Y. J. Chen, 2010, 2010 IEEE International Reliability Physics Symposium.

A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Junction optimization for Reliability issues in floating gate NAND flash cells

Chih-Yuan Lu, Tahui Wang, C. H. Lee, 2011, 2011 International Reliability Physics Symposium.

A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications

Chih-Yuan Lu, Tahui Wang, T.C. Lu, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

FOUP mini-environment contaminants analysis in semiconductor manufacturing

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2014, 2014 e-Manufacturing & Design Collaboration Symposium (eMDC).

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

Chih-Yuan Lu, Tahui Wang, Wen-Jer Tsai, 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D NAND Flash Architecture and Studies of Bottom Source Engineering

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Enhanced PMOS-triggered PMLSCR with robust EOS immunity

Yao-Wen Chang, Chih-Yuan Lu, Kuang-Chao Chen, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

RTN modulation by neighboring word-line Vt level in 1Xnm floating gate NAND strings

Chih-Yuan Lu, Tahui Wang, Y.H. Chen, 2018, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A novel dichotomic programming algorithm applied to 3D NAND flash

Chih-Yuan Lu, Hsiang-Pang Li, Hang-Ting Lue, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Modeling of Apparent Activation Energy and Lifetime Estimation for Retention of 3D SGVC Memory

Chih-Yuan Lu, Nian-Jia Wang, Wei-Hao Hsiao, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Study of Intra-Nitride Charge Transport of SONOS-Type Devices using Gate-Sensing and Channel-Sensing Transient Analysis Method

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage

Chih-Yuan Lu, Hsiang-Pang Li, Yi-Hsuan Hsiao, 2013, 2013 Symposium on VLSI Technology.

A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Investigations on elimination of plasma-induced Si substrate damage for 3D NAND fabrication: AEPM: Advanced equipment processes and materials

Chih-Yuan Lu, Zusing Yang, Chih-Yao Lin, 2017, ASMC 2017.

A non-typical latch-up event on HV ESD protection

Yao-Wen Chang, Chih-Yuan Lu, Kuang-Chao Chen, 2014, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014.

A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Chih-Yuan Lu, Yi-Hsuan Hsiao, Hang-Ting Lue, 2010, 2010 IEEE International Memory Workshop.

Excellent resistance variability control of WOx ReRAM by a smart writing algorithm

Chih-Yuan Lu, Yu-Hsuan Lin, Jau-Yi Wu, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Blind contact detection in the irregularly periphery area using leap & scan e-beam inspection

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2011, 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM).

Pattern dependent satellite defects in via lithography

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2012, Other Conferences.

A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

Chih-Yuan Lu, J.S. Huang, Wen-Jer Tsai, 2008, 2008 IEEE International Reliability Physics Symposium.

Gate stack etch induced reliability issues in nitrided-based trapping storage cells

Chih-Yuan Lu, Tahui Wang, Y. J. Chen, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Wafer-edge defect reduction for tri-layer materials in BEOL applications

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2011, Advanced Lithography.

A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming

Chih-Yuan Lu, Hang-Ting Lue, Tzu-Hsuan Hsu, 2013, 2013 Symposium on VLSI Technology.

Image-assistant OPC model calibration on 65nm node contact layer

Chih-Yuan Lu, Y. Y. Tsai, Fred Lo, 2009, Advanced Lithography.

A Novel Confined Nitride-Trapping Layer Device for 3D NAND Flash with Robust Retention Performances

Chih-Yuan Lu, Hang-Ting Lue, Wei-Chen Chen, 2019, 2019 Symposium on VLSI Technology.

Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Chih-Yuan Lu, Rich Liu, Hang-Ting Lue, 2010, IEEE Transactions on Device and Materials Reliability.

Study of the charge-trapping characteristics of silicon-rich nitride thin films using the gate-sensing and channel-sensing (GSCS) method

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2009, 2009 IEEE International Reliability Physics Symposium.

Highly scalable NAND-type PHINES flash memory for data flash applications

Chih-Yuan Lu, T.C. Lu, W.J. Tsai, 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.

3D AND-type NVM for In-Memory Computing of Artificial Intelligence

Chih-Yuan Lu, Hang-Ting Lue, Keh-Chung Wang, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Post etch killer defect characterization and reduction in a self-aligned double patterning technology

Chih-Yuan Lu, Sheng-Yuan Chang, Hong-Ji Lee, 2011, 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Chih-Yuan Lu, Ya-Chin King, Hang-Ting Lue, 2016, IEEE Transactions on Electron Devices.

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Chih-Yuan Lu, Ya-Chin King, Hang-Ting Lue, 2015, IEEE Electron Device Letters.

A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

Shih-Hung Chen, Chih-Yuan Lu, Kuo-Pin Chang, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Inspection flow of yield impacting systematic defects

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2013, 2013 e-Manufacturing & Design Collaboration Symposium (eMDC).

A new methodology for assessment of the susceptibility to data retention in floating gate non-volatile memories

Chih-Yuan Lu, Kuang-Chao Chen, Ming-Yi Lee, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Field effect transistor with gate separator.

Kuo-Hua Lee, Chih-Yuan Lu, Janmye Sung, 1990 .

A novel two-step poly CMP to improve dishing and erosion effect on self-aligned floating gate process

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2011, 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM).

Reduction of wafer arcing during high aspect ratio etching

Chih-Yuan Lu, Zusing Yang, Min-Feng Hung, 2017, 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

The application of e beam inspection on 3D NAND flash

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2012, 2012 e-Manufacturing & Design Collaboration Symposium (eMDC).

Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics

Chih-Yuan Lu, Kuo-Pin Chang, Tahone Yang, 2012, 2012 4th IEEE International Memory Workshop.

A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application

Chih-Yuan Lu, Hung-Sheng Chang, Hang-Ting Lue, 2018, 2018 IEEE Symposium on VLSI Technology.

Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering

Chih-Yuan Lu, Rich Liu, Ya-Chin King, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization

Chih-Yuan Lu, Zusing Yang, Sheng-Yuan Chang, 2018, 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Contact formation with extremely low proximity effect by double patterning technology

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2009, Advanced Lithography.

Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

Overview of 3D NAND Flash and progress of vertical gate (VG) architecture

Shih-Hung Chen, Chih-Yuan Lu, Hang-Ting Lue, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2008, IEEE Transactions on Device and Materials Reliability.

Yield enhancement using source/drain BF2+ implant process optimization

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Trapping-free string select transistors and ground select transistors for Vg-type 3D NAND Flash memory

Chih-Yuan Lu, Tahone Yang, Mars Yang, 2014, 2014 IEEE 6th International Memory Workshop (IMW).

Sensitivities improvement by utilizing dark mode of bright filed inspection

Chih-Yuan Lu, Tahone Yang, Tuung Luoh, 2012, 2012 e-Manufacturing & Design Collaboration Symposium (eMDC).

Methods of removing solvent-like residues from wafer backside bevel

Chih-Yuan Lu, Sheng-Yuan Chang, Hong-Ji Lee, 2013, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.

Process optimization by advanced process control with fault detection system for flash memory

Chih-Yuan Lu, Kuang-Chao Chen, Tuung Luoh, 2004, 2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846).

Optimization and monitoring of bevel removal process

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2011, 2011 e-Manufacturing & Design Collaboration Symposium & International Symposium on Semiconductor Manufacturing (eMDC & ISSM).

Investigation of shape etching on multi-layer SiO2/poly-Si for 3D NAND architecture

Chih-Yuan Lu, Zusing Yang, Hong-Ji Lee, 2013, ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference.

study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash

Chih-Yuan Lu, R. Liu, Hang-Ting Lue, 2008, 2008 IEEE International Reliability Physics Symposium.

SMO and NTD for robust single exposure solution on contact patterning for 40nm node flash memory devices

Chih-Yuan Lu, Elvis Yang, T. H. Yang, 2013, Advanced Lithography.

Variable loading kernels for OPC modeling

Chih-Yuan Lu, Fred Lo, Elvis Yang, 2008, SPIE Advanced Lithography.

An Approach of 3D NAND Flash Based Nonvolatile Computing-In-Memory (nvCIM) Accelerator for Deep Neural Networks (DNNs) with Calibration and Read Disturb Analysis

Chih-Yuan Lu, Hang-Ting Lue, Chih-Chang Hsieh, 2020, 2020 IEEE International Memory Workshop (IMW).

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Shih-Hung Chen, Chih-Yuan Lu, Kuo-Pin Chang, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A Novel Gate-Injection Program/Erase P-Channel NAND-Type Flash Memory with High (10M Cycle) Endurance

Chih-Yuan Lu, Tahone Yang, Kuang-Chao Chen, 2007, 2007 IEEE Symposium on VLSI Technology.

PMOS-triggered PMLSCR for high voltage application

Yao-Wen Chang, Chih-Yuan Lu, Kuang-Chao Chen, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture

Chih-Yuan Lu, Hang-Ting Lue, Kuang-Yeu Hsieh, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Pre-Epitaxial Plasma Etch Treatment for the Selective Epitaxial Growth of Silicon in High Aspect Ratio 3D NAND Memory

Chih-Yuan Lu, Hong-Ji Lee, Nan-Tzu Lian, 2019, 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).