Vinayaka Jyothi

Design and analysis of ring oscillator based Design-for-Trust technique

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2011, 29th VLSI Test Symposium.

DPFEE: A High Performance Scalable Pre-Processor for Network Security Systems

Ramesh Karri, Vinayaka Jyothi, Sateesh K. Addepalli, 2018, IEEE Transactions on Multi-Scale Computing Systems.

FPGA Trust Zone: Incorporating trust and reliability into FPGA designs

Ramesh Karri, Vinayaka Jyothi, Richard Stern, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Intra-die process variation aware anomaly detection in FPGAs

Matthew French, Vinayaka Jyothi, Youngok Pino, 2014, 2014 International Test Conference.

Blue team red team approach to hardware trust assessment

Jeyavijayan Rajendran, Ramesh Karri, Vinayaka Jyothi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks

Ramesh Karri, Xueyang Wang, Sateesh Addepalli, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems

Ramesh Karri, Sateesh Addepalli, Vinayaka Jyothi, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Fingerprinting Field Programmable Gate Arrays

Ramesh Karri, Vinayaka Jyothi, Richard Stern, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

TAINT: Tool for Automated INsertion of Trojans

Ramesh Karri, Prashanth Krishnamurthy, Farshad Khorrami, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Hardware Trojan Attacks in FPGA and Protection Approaches

Jeyavijayan Rajendran, Vinayaka Jyothi, 2018 .