Jeongho Hwang

A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

D. Jeong, Kwanseo Park, Kwangho Lee, 2021, IEEE Journal of Solid-State Circuits.

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

D. Jeong, Wooseok Kim, Taeik Kim, 2018, 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS).

Test of the VCSEL driver based on Verilog-A VCSEL model

Yoonsoo Kim, Gyungock Kim, D. Jeong, 2015, 2015 International SoC Design Conference (ISOCC).

32.4 A 0.4-to-1.2V 0.0057mm2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement

Deog-Kyoon Jeong, Jun-Eun Park, Jonghyun Oh, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS

Deog-Kyoon Jeong, Gyu-Seob Jeong, Jeongho Hwang, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.