R. Halbach

Impact of stress engineering on high-k metal gate ESD diodes in 32nm SOI technology

C. Putnam, R. Gauthier, S. Mitra, 2009, 2009 31st EOS/ESD Symposium.

Electrically Programmable Fuses for Analog and Mixed Signal Applications in Silicon Germanium BiCMOS Technologies

T. Kirihata, D. Coolbaugh, D. Coolbaugh, 2007, 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology

R. Gauthier, C. Seguin, S. Mitra, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

K. Chatty, C. Seguin, R. Halbach, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

On The Interaction of ESD, NBTI and HCI in 65nm Technology

R. Gauthier, K. Chatty, C. Seguin, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.