M. DeHerrera
发表
T. Andre,
J. Janesky,
D. Shum,
2017,
2017 Symposium on VLSI Technology.
Jon M. Slaughter,
Saied N. Tehrani,
J. Janesky,
2000
.
T. Andre,
J. Janesky,
S. Deshpande,
2013,
2013 5th IEEE International Memory Workshop.
P. Brown,
S. Zoll,
J. Nahas,
2005,
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
T. Andre,
J. Janesky,
D. Shum,
2016,
2016 IEEE International Electron Devices Meeting (IEDM).
M. Durlam,
M. DeHerrera,
G. Grynkewich,
2007,
2007 IEEE International Conference on Integrated Circuit Design and Technology.
P. Brown,
M. Durlam,
J. Janesky,
2004,
IEEE Transactions on Device and Materials Reliability.
Saied N. Tehrani,
Jing Shi,
M. DeHerrera,
1999
.
P. Brown,
M. Durlam,
J. Janesky,
2004,
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
Saied N. Tehrani,
J. Janesky,
M. DeHerrera,
2002
.
B. Hughes,
J. Janesky,
K. Nagel,
2019,
2019 IEEE International Electron Devices Meeting (IEDM).
P. Brown,
M. Durlam,
J. Janesky,
2003,
IEEE International Electron Devices Meeting 2003.
Saied N. Tehrani,
A. Omair,
M. DeHerrera,
2003,
IEEE J. Solid State Circuits.
M. DeHerrera,
J.M. Slaughter,
S. Tehrani,
2006,
IEEE Transactions on Magnetics.
M. Durlam,
J. Janesky,
M. DeHerrera,
2007,
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).