S. M. Alam

CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications

T. Andre, J. Janesky, D. Shum, 2017, 2017 Symposium on VLSI Technology.

Non-destructive variability tolerant differential read for non-volatile logic

S. M. Alam, J. Das, S. Bhanja, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

A novel design concept for high density hybrid CMOS-nanomagnetic circuits

S. M. Alam, J. Das, S. Bhanja, 2012, 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO).

Addressing the layout constraint problem when cascading logic gates in nanomagnetic logic

S. M. Alam, J. Das, S. Bhanja, 2012, 2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO).

High density ST-MRAM technology (Invited)

T. Andre, J. Janesky, S. Deshpande, 2012, 2012 International Electron Devices Meeting.

Technology for reliable spin-torque MRAM products

T. Andre, J. Janesky, D. Shum, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Demonstration of a Reliable 1 Gb Standalone Spin-Transfer Torque MRAM For Industrial Applications

B. Hughes, J. Janesky, K. Nagel, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Circuit and System Level Tools for Thermal-Aware Reliability Assessments of IC Designs Project

S. M. Alam, C. V. Thompson, D. E. Troxel, 2005 .