Teva Stone

A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces

Jared Zerbe, Barry Daly, Lei Luo, 2010, 2010 Symposium on VLSI Circuits.

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

Yue Lu, Lei Luo, Jared Zerbe, 2011, IEEE Journal of Solid-State Circuits.

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems

Yi Lu, Lei Luo, Barry Daly, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems

Yi Lu, Lei Luo, Barry Daly, 2014, IEEE Journal of Solid-State Circuits.

A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI

Lei Luo, Barry Daly, Teva Stone, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

Masum Hossain, Jared Zerbe, Barry Daly, 2014, IEEE Journal of Solid-State Circuits.

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

Masum Hossain, Jared Zerbe, Barry Daly, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface

Jared Zerbe, Barry Daly, John Eble, 2013, 2013 Symposium on VLSI Circuits.

A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on

Jared Zerbe, Barry Daly, Wayne Dettloff, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.