Chung-Bin Wu

Simple Impulse Noise Cancellation Based on Fuzzy Logic

J. Yang, Bin-Da Liu, Chung-Bin Wu, 2003 .

Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator

Chung-Bin Wu, Yu-Kuan Hsiao, Wei-Hsuan Chang, 2022, 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator

Y. Hwang, Chung-Bin Wu, Yu-Kuan Hsiao, 2020, 2020 International SoC Design Conference (ISOCC).

Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator

Chung-Bin Wu, Ching-Shun Wang, Yu-Kuan Hsiao, 2020, 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE).

High Throughput Hardware Implementation for Deep Learning AI Accelerator

Chung-Bin Wu, Yu-Cheng Hsueh, Ching-Shun Wang, 2019, 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).

Adaptive postprocessors with DCT-based block classifications

Jar-Ferr Yang, Bin-Da Liu, Chung-Bin Wu, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Ultra-Low Complexity Block-Based Lane Detection and Departure Warning System

Chung-Bin Wu, Li-Hung Wang, Kuan-Chieh Wang, 2019, IEEE Transactions on Circuits and Systems for Video Technology.

A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC

Chih-Peng Fan, Chung-Bin Wu, Chia-Wei Chang, 2015, Journal of Signal Processing Systems.

A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC

Chih-Peng Fan, Chung-Bin Wu, Hao-Fan Hsu, 2016, J. Signal Process. Syst..