Yu-Liang Wu

发表

Methodology of Forecasting the Developing Tendency of a GIS PD Based on the Fractal Dimension and Catastrophe Theory

Y. Quan, Bo Yi, Yu-Liang Wu, 2014 .

To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO

Yu-Liang Wu, Xing Wei, Yi Diao, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Yu-Liang Wu, Hongbing Fan, Hongbing Fan, 2008, FCS.

A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability

Yu-Liang Wu, Wai-Chung Tang, Catherine L. Zhou, 2008, ERSA.

Decidability of Irreducible Tree Shifts of Finite Type

J. Ban, Chih-Hung Chang, Yu-Liang Wu, 2019, Journal of Statistical Physics.

On optimum switch box designs for 2-D FPGAs

Jiping Liu, Hongbing Fan, Yu-Liang Wu, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Topologically Mixing Properties of Multiplicative Integer Systems

J. Ban, Chih-Hung Chang, Yu-Liang Wu, 2019, Real Analysis Exchange.

Spectral measures with arbitrary dimensions

Yu-Liang Wu, Zhiyi Wu, 2022, 2204.13549.

Comment on Generic Universal Switch Blocks

Yu-Liang Wu, Yao-Wen Chang, Hongbing Fan, 2002, IEEE Trans. Computers.

Graph based analysis of 2-D FPGA routing

Malgorzata Marek-Sadowska, Shuji Tsukiyama, Yu-Liang Wu, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Mathematical Analysis of Spread Models: From the viewpoints of Deterministic and random cases

Chih-Hung Chang, Yu-Liang Wu, Jung-Chao Ban, 2021 .

A dual-mode built-in self-test technique for capacitive MEMS devices

Wen-Ben Jone, Yu-Liang Wu, Xingguo Xiong, 2004, IEEE Transactions on Instrumentation and Measurement.

Optimal MST-based graph algorithm on FPGA segmentation design

C.L. Zhou, Yu-Liang Wu, Yu-Liang Wu, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

On optimal hyperuniversal and rearrangeable switch box designs

Yu-Liang Wu, Jiping Liu, Hongbing Fan, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing

Malgorzata Marek-Sadowska, Yu-Liang Wu, M. Marek-Sadowska, 1995, 32nd Design Automation Conference.

On applying erroneous clock gating conditions to further cut down power

Yu-Liang Wu, Xiaoqing Yang, Tak-Kei Lam, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Logic synthesis for low power using clock gating and rewiring

Steve Yang, Yu-Liang Wu, Tak-Kei Lam, 2010, GLSVLSI '10.

An efficient router for 2-D field programmable gate array

Malgorzata Marek-Sadowska, Yu-Liang Wu, M. Marek-Sadowska, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Algorithms and Implementation for Interconnection Graph Problem

Yu-Liang Wu, Jason B. Ernst, Christian Rosenke, 2008, COCOA.

Scan-based BIST using an improved scan forest architecture

Dong Xiang, Yu-Liang Wu, Kaiwei Li, 2004, 13th Asian Test Symposium.

Customized Reconfigurable Interconnection Networks for multiple application SOCS

Yu-Liang Wu, Jason B. Ernst, Jason Ernst, 2008, 2008 International Conference on Field Programmable Logic and Applications.

R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip

Yu-Liang Wu, Hongbing Fan, Yue-Ang Chen, 2012, ARC.

Design Automation Framework for Reconfigurable Interconnection Networks

Yu-Liang Wu, Ray C. C. Cheung, Hongbing Fan, 2013, Comput. J..

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

Yu-Liang Wu, Wai-Chung Tang, Catherine L. Zhou, 2007, 2007 44th ACM/IEEE Design Automation Conference.

The exact channel density and compound design for generic universal switch blocks

Yu-Liang Wu, Jiping Liu, Hongbing Fan, 2007, TODE.

Decomposition design theory and methodology for arbitrary-shaped switch boxes

Yu-Liang Wu, Ray C. C. Cheung, Jiping Liu, 2006, IEEE Transactions on Computers.

Crossbar based design schemes for switch boxes and programmable interconnection networks

Yu-Liang Wu, Hongbing Fan, Hongbing Fan, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Augmented disjoint switch boxes for FPGAs

Yu-Liang Wu, Hongbing Fan, Catherine L. Zhou, 2005 .

On Optimal Irregular Switch Box Designs

Yu-Liang Wu, Jiping Liu, Hongbing Fan, 2004, FPL.

What if merging connection and switch boxes - an experimental revisit on FPGA architectures

C.L. Zhou, Yu-Liang Wu, R.C.C. Cheung, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

Reduction design for generic universal switch blocks

Chak-Kuen Wong, Yu-Liang Wu, Jiping Liu, 2002, TODE.

On Optimum Designs of Universal Switch Blocks

Yu-Liang Wu, Jiping Liu, Hongbing Fan, 2002, FPL.

General Models and a Reduction Design Technique for FPGA Switch Box Designs

Yu-Liang Wu, Jiping Liu, Hongbing Fan, 2003, IEEE Trans. Computers.

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)

Yu-Liang Wu, Xing Wei, Tak-Kei Lam, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).