Go Matsukawa

发表

An soft error propagation analysis considering logical masking effect on re-convergent path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

An accurate soft error propagation analysis technique considering temporal masking disablement

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015 .

FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2018, IEICE Electronics Express.

A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations

Shintaro Izumi, Masahiko Yoshimoto, Daisuke Watanabe, 2020, IEEE Journal of Selected Topics in Signal Processing.

A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2015, IEICE Trans. Electron..

A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2014, ARCS Workshops.

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video

Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, 2017, IEICE Electron. Express.