Srivatsan Parthasarathy

发表

A transient triggered bipolar clamp for electrostatic discharge protection in SiGe BiCMOS technologies

Javier A. Salcedo, Jean-Jacques Hajjar, Srivatsan Parthasarathy, 2013, 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM).

In Situ ESD Protection Structure for Variable Operating Voltage Interface Applications in 28-nm CMOS Process

Sirui Luo, Javier A. Salcedo, Jean-Jacques Hajjar, 2014, IEEE Transactions on Device and Materials Reliability.

Design optimization of SiGe BiCMOS Silicon Controlled Rectifier for Charged Device Model (CDM) protection applications

Javier A. Salcedo, Jean-Jacques Hajjar, Yuanzhong Zhou, 2014, Microelectron. Reliab..

Balancing the Trade-off Between Performance and Mis-trigger Immunity in Active Feedback-based High-voltage Tolerant Power Clamps

Jean-Jacques Hajjar, Elyse Rosenbaum, Srivatsan Parthasarathy, 2020, 2020 42nd Annual EOS/ESD Symposium (EOS/ESD).

ESD protection structure with reduced capacitance and overshoot voltage for high speed interface applications

Sirui Luo, Javier A. Salcedo, Jean-Jacques Hajjar, 2017, Microelectron. Reliab..

CDM event simulation in SPICE: A holistic approach

Jean-Jacques Hajjar, Yuanzhong Zhou, Thorsten Weyl, 2011, EOS/ESD Symposium Proceedings.

Monolithic ESD protection for distributed high speed applications in 28-nm CMOS technology

Javier A. Salcedo, Jean-Jacques Hajjar, Srivatsan Parthasarathy, 2014, 2014 IEEE International Reliability Physics Symposium.

ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process

Javier A. Salcedo, Jean-Jacques Hajjar, Srivatsan Parthasarathy, 2015, 2015 IEEE International Reliability Physics Symposium.

Design of ESD protection for large signal swing RF inputs operating to 24GHz in 0.18um SiGe BiCMOS process

Srivatsan Parthasarathy, J.-J Hajjar, Javier Salcedo, 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

Snapback and Postsnapback Saturation of Pseudomorphic High-Electron Mobility Transistor Subject to Transient Overstress

Yuanzhong Zhou, Qiang Cui, Srivatsan Parthasarathy, 2010, IEEE Electron Device Letters.

Embedded shunt diode pair to suppress overshoot voltage

Javier A. Salcedo, Jean-Jacques Hajjar, Juin J. Liou, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Interfacing AC Coupled Interconnect design with Rocket I/O compatible FPGA systems.

Srivatsan Parthasarathy, 2006 .

High blocking voltage ESD timer clamp with mis-trigger protection

Javier A. Salcedo, Jean-Jacques Hajjar, Srivatsan Parthasarathy, 2017, 2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

System Level Esd Simulation In Spice: A Holistic Approach

Jean-Jacques Hajjar, Dave Clarke, Yuanzhong Paul Zhou, 2018, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Distributed ESD Protection Network for Millimetre-Wave RF Applications

Hang Li, Javier A. Salcedo, Jean-Jacques Hajjar, 2018, 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

High mobility SiGe shell-Si core omega gate pFETS

Ji-Woon Yang, Raj Jammy, Bich-Yen Nguyen, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Extraction of AlGaN/GaN HEMT Gauge Factor in the Presence of Traps

Toshikazu Nishida, Srivatsan Parthasarathy, Scott E Thompson, 2010, IEEE Electron Device Letters.

Design of a low leakage ESD clamp for high voltage supply in 65nm CMOS technology

Javier A. Salcedo, Jean-Jacques Hajjar, Srivatsan Parthasarathy, 2014, 2014 IEEE International Reliability Physics Symposium.