S.W. Sun

Symmetrical 45nm PMOS on [110] substrate with excellent S/D extension distribution and mobility enhancement

C.H. Hsu, J.R. Hwang, J.H. Ho, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A Novel RF-WAT Test Structure for Advanced Process Monitoring in SOC Applications

R. Lee, Mao Chyuan Tang, C.S. Yeh, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

A novel fabrication process to downscale SiON gate dielectrics (EOT = 1.06 nm, Jgn = 8.5 A/cm/sup 2/) toward sub-65nm and beyond

M.F. Lu, S.W. Sun, W.T. Chiang, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications

D. Wristers, L.W. Cheng, S.C. Chien, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering

S.C. Chien, Y.C. Liu, S.W. Sun, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach

L.W. Cheng, S.C. Chien, Y.S. Hsieh, 2008, 2008 IEEE International Electron Devices Meeting.

A novel 0.25 /spl mu/m shallow trench isolation technology

S.W. Sun, W. Lur, S. Sun, 1996, International Electron Devices Meeting. Technical Digest.

A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing

S.Y. Hsu, S.W. Sun, M.J. Tsai, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology

S.W. Sun, Y. Yoshii, M. Kearney, 1986, 1986 International Electron Devices Meeting.