Chushin Afuso

A Study of Binarization Method for Character Image Taken with CCD Camera

Ginga Nagamine, Tsuyoshi Yamashiro, Chushin Afuso, 1997 .

A universal literal circuit and its application to quaternary logic networks

Makoto Honda, Yasunori Nagata, Chotei Zukeran, 1992, Systems and Computers in Japan.

An Optimum Half-Hot Code Assignment Algorithm for Input Encoding and Its Application to Finite State Machines

Masao Mukaidono, Yasunori Nagata, Chushin Afuso, 1995, IEICE Trans. Inf. Syst..

A method of test pattern generation for multiple-valued PLAs

Yasunori Nagata, Chushin Afuso, 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

Design of low-power quaternary CMOS logic circuits

Michitaka Kameyama, Tatsuo Higuchi, Chotei Zukeran, 1986, Systems and Computers in Japan.

A State Assignment for p-Valued Sequential Machines

Yasunori Nagata, Chotei Zukeran, Chushin Afuso, 1990, Systems and Computers in Japan.

Design of a low‐power universal literal circuit

Chotei Zukeran, Chushin Afuso, Shin-ichiro Tsuhako, 1993 .

A FAULT MODEL FOR MULTIVALUED PLA`S

Yasunori Nagata, Chushin Afuso, 1992 .

Design of micropower CMOS quaternary memory circuits

Michitaka Kameyama, Tatsuo Higuchi, Chotei Zukeran, 1987, Systems and Computers in Japan.