K. Nehru

Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits

K. Nehru, A. Shanmugam, S. Vadivel, 2012, 2012 International Conference on Computing, Communication and Applications.

Design of low power ALU using 8T FA and PTL based MUX circuits

K. Nehru, A. Shanmugam, G. Darmila Thenmozhi, 2012, IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012).

Ber Analysis of Swt Based Ofdm on Lte

K. Nehru, T. Nagarjuna, G. Nagendra Prasad, 2020 .

CLRCL Full Adder based Low Power Multiplier Architectures

K. Nehru, A. Shanmugam, S. Vadivel, 2012 .

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

K. Nehru, T. Nagarjuna, G. Vijay, 2017 .

Certain investigations on arithmetic sub systems in low power VLSI

K. Nehru, 2014 .

Design of 16 Bit Vedic Multiplier Using Semi-Custom and Full Custom Approach

K. Nehru, T. T. Linju, 2017 .

A Shannon Based Low Power Adder Cell for Neural Network Training

K. Nehru, A. Shanmugam, S. Deepa, 2010 .