K. Maex

发表

Development And Evaluation Of CoSi2 Schottky Barrier Infrared Detectors

C. Claeys, J. Kurianski, J. Vermeiren, 1990, Optics & Photonics.

A yield-aware modeling methodology for nano-scaled SRAM designs

W. Dehaene, K. Maex, E. Grossar, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

Technology aware design and design aware technology

W. Dehaene, K. Maex, F. Catthoor, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

Energy-Aware and Application Dependent Optimization of On-Chip Micro-strip Transmission Lines

K. Maex, M. Stucchi, M. Bamal, 2006, 2006 IEEE Workship on Signal Propagation on Interconnects.

Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies

W. Dehaene, K. Maex, E. Grossar, 2006, IEEE Journal of Solid-State Circuits.

Salicides for 0.18 um and below

K. Maex, 1998, 28th European Solid-State Device Research Conference.

On a More Accurate Assessment of Scaled Copper/Low-k Interconnects Performance

M. Van Hove, K. Maex, M. Stucchi, 2007, IEEE Transactions on Semiconductor Manufacturing.

Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes

M. Van Hove, K. Maex, M. Stucchi, 2006, 2006 International Interconnect Technology Conference.

New analytic expressions for mutual inductance and resistance of coupled interconnects on lossy silicon substrate

S. Vandenberghe, B. Nauwelaers, K. Maex, 2001, 2001 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers (IEEE Cat. No.01EX496).

Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

M. Van Hove, S. Demuynck, K. Maex, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

C. Vrancken, A. Veloso, S. Biesemans, 2006, IEEE Electron Device Letters.

Impact of the barrier/dielectric interface quality on reliability of Cu porous-low-k interconnects

S. Demuynck, P. Roussel, K. Maex, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

K. Maex, I. Ciofi, Z. Tokei, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Some measurement results for frequency-dependent inductance of IC interconnects on a lossy silicon substrate

S. Vandenberghe, D. Schreurs, B. Nauwelaers, 2002, IEEE Electron Device Letters.

High-Q RF inductors on standard silicon realized using wafer-level packaging techniques

E. Beyne, S. Decoutere, W. De Raedt, 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

Diffusion barrier integrity and electrical performance of Cu/porous dielectric damascene lines

K. Maex, M. Stucchi, F. Iacopi, 2003, IEEE Electron Device Letters.

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

S. Decoutere, B. Nauwelaers, S. Jenei, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Wafer-level packaging technology for extended global wiring and inductors

E. Beyne, S. Decoutere, W. De Raedt, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process

M. Van Hove, K. Maex, H. Meynen, 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Modulation of the workfunction of Ni fully silicided gates by doping: dielectric and silicide phase effects

K. Maex, T. Janssens, K.G. Anil, 2006, IEEE Electron Device Letters.

Self-aligned gined CoSi2 in a Submicron CMOS Process

K. Maex, L. Van den hove, R.A.M. Wolters, 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

Add-on Cu/SiLK/sup TM/ module for high Q inductors

S. Decoutere, B. Nauwelaers, S. Jenei, 2002, IEEE Electron Device Letters.

Silicide induced pattern density and orientation dependent transconductance in MOS transistors

K. Maex, M. Stucchi, A. Steegen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Shallow Junction Formation using CoSi2 as a Diffusion Source

K. Maex, H. Schaber, V. Probst, 1987, ESSDERC '87: 17th European Solid State Device Research Conference.

The isocurrent test: a promising tool for wafer-level evaluation of the interconnect reliability

K. Maex, D. Wouters, M. Van Dievel, 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

Challenges of clean/strip processing for Cu/low-k technology

W. Boullart, K. Maex, H. Struyf, 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

Local mechanical stress induced defects for Ti and Co/Ti silicidation in sub-0.25 /spl mu/m MOS-technologies

I. De Wolf, K. Maex, A. Steegen, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

The influence of surface fluctuations on early failures in single-damascene Cu wires: A Weakest Link Approximation analysis

K. Maex, C. Bruynseraede, H. Wang, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

The impact of scaling on interconnect reliability

J. Michelon, K. Maex, Z. Tokei, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..