I. Takanami

Built-in self-repairable cube-connected cycles architectures and their reliability analyses

I. Takanami, K. Kurata, 1994, Proceedings of IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems.

Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides

I. Takanami, K. Inoue, Y. Hisanaga, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

I. Takanami, T. Watanabe, K. Kurata, 1995, Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI).

A decoder for DEC-TED BCH codes

I. Takanami, H. Okano, K. Morikawa, 1984 .

A two-way nondetereministic one-counter languages not accepted by nondeterministic rebound automata

I. Takanami, M. Sakamoto, K. Inoue, 1990 .

A note on alternating turing machines using small space

I. Takanami, A. Ito, K. Inoue, 1987 .

Fault test for cellular arrays realizing multi-valued logic functions

I. Takanami, 井上 克司, 1989 .

Some realizations of multi-valued logic functions with cellular arrays

I. Takanami, K. Inoue, 1989 .