K. Miyashita

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

J. Bonnouvrier, R. Augur, F. Arnaud, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

46.1: Invited Paper: Interface — The Key to High‐Performance Poly‐Si TFT Fabrication

T. Shimoda, S. Higashi, T. Kawamura, 2003 .

Development of high-performance polycrystalline silicon thin-film transistors (TFTs) using defect control process technologies

T. Shimoda, S. Higashi, T. Kawamura, 2002, IEEE Electron Device Letters.

High-Quality SiO2/Si Interface Formation and Its Application to Fabrication of Low-Temperature-Processed Polycrystalline Si Thin-Film Transistor

T. Shimoda, S. Higashi, T. Kawamura, 2002 .

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

An 80 nm dual-gate CMOS with shallow extensions formed after activation annealing and SALICIDE

H. Kawashima, E. Morifuji, Y. Toyoshima, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Optimized halo structure for 80 nm physical gate CMOS technology with indium and antimony highly angled ion implantation

M. Takayanagi, Y. Toyoshima, M. Fujiwara, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors

J. Koga, Y. Toyoshima, F. Matsuoka, 2006, 2006 International Electron Devices Meeting.