G. Mueller

Detection and classification of explosive compounds utilizing laser ion mobility spectrometry

A. Langmeier, W. Heep, C. Oberhuettinger, 2009, Defense + Commercial Sensing.

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

G. Daniel, D. Hanson, M. Wordeman, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

T. Kirihata, H. Terletzki, C. Radens, 2000, IEEE Journal of Solid-State Circuits.

Slotted vias for dual damascene interconnects in 1 Gb DRAMs

R. Filippi, C. Lin, G. Mueller, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

G. Daniel, M. Wordeman, T. Kirihata, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 16Mb MRAM featuring bootstrapped write drivers

H. Hoenigschmid, G. Mueller, W.J. Gallagher, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 16-Mb MRAM featuring bootstrapped write drivers

H. Hoenigschmid, G. Mueller, W.J. Gallagher, 2005, IEEE Journal of Solid-State Circuits.