Shin'ichiro Okazaki

发表

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai, 2005, ISCA 2005.

IMPACAR2: A SIMD/MIMD Dynamically Switchable Processor For In-Vehicle Image Recognition System

Shorin Kyo, Shin'ichiro Okazaki, Hanno Lieske, 2008 .

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2003 .

An Integrated Memory Array Processor for Embedded Image Recognition Systems

Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai, 2007, IEEE Transactions on Computers.

IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

A 3.84 gips integrated memory array processor

Shin'ichiro Okazaki, Yoshihiro Fujita, Kazuyuki Nakamura, 1996, Syst. Comput. Jpn..

A low-cost mixed-mode parallel processor architecture for embedded systems

Shorin Kyo, Shin'ichiro Okazaki, Hanno Lieske, 2007, ICS '07.

A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems

Shorin Kyo, Shin'ichiro Okazaki, Shouhei Nomoto, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Imap: Integrated Memory Array Processor

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1992, J. Circuits Syst. Comput..

A real-time vision system using an integrated memory array processor prototype

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 2005, Machine Vision and Applications.

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

Shorin Kyo, Shin'ichiro Okazaki, 2011, J. Signal Process. Syst..

An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1996, Proceedings of 13th International Conference on Pattern Recognition.

A 51.2GOPS Programmable Video Recognition Processor for Vision Based Intelligent Cruise Control Applications

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2002, MVA.

A Video Recognition Processor for Intelligent Cruise Control Based on 128 4-Way VLIW RISC Processing Elements

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2003 .

IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1996, MVA.

CREATING AN OPEN, FLEXIBLE, COST-EFFICIENT ARCHITECTURE FRAMEWORK FOR THE PAYMENT OF TELEMATICS SERVICES

Shorin Kyo, Shin'ichiro Okazaki, F. Hidano, 2006 .

IMAP: Integrated Memory Array Processor-Toward a GIPS Order SIMD Processing LSI (Special Issue on New Architecture LSIs)

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1993 .

Efficient data transfer operations for a SIMD processor array system

Yuki Kobayashi, Shorin Kyo, Shin'ichiro Okazaki, 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor

Shorin Kyo, Shin'ichiro Okazaki, Kazuyuki Sakurai, 2007, IEICE Trans. Inf. Syst..

Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors

Shorin Kyo, Shin'ichiro Okazaki, Shouhei Nomoto, 2009, 2009 Third ACM/IEEE International Conference on Distributed Smart Cameras (ICDSC).

An integrated memory array processor architecture for embedded image recognition systems

Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai, 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1992, MVA.

An Integrated Memory Array Processor and a Real-Time Vision System

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1995 .

IMAP-CE A 51.2GOPS video rate image processor with 128 VLIW processing elements : Special issue on recent recognition technologies

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2002 .

A programmable parallel processor LSI for video-based driver assistance systems

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 2003, Proceedings of the 2003 IEEE International Conference on Intelligent Transportation Systems.

A Compact 30GIPS Real-Time Vision System RVS-2

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1994, MVA.

A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system

Shin'ichiro Okazaki, Y. Fujita, N. Yamashita, 1995, Proceedings of Conference on Computer Architectures for Machine Perception.

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

Shorin Kyo, Shin'ichiro Okazaki, Shouhei Nomoto, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

A robust vehicle detecting and tracking system for wet weather conditions using the IMAP-VISION image processing board

Shorin Kyo, Shin'ichiro Okazaki, Takuya Koga, 1999, Proceedings 199 IEEE/IEEJ/JSAI International Conference on Intelligent Transportation Systems (Cat. No.99TH8383).

In-vehicle vision processors for driver assistance systems

Shorin Kyo, Shin'ichiro Okazaki, S. Kyo, 2008, 2008 Asia and South Pacific Design Automation Conference.

A compact real-time vision system using integrated memory array processor architecture

Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita, 1995, IEEE Trans. Circuits Syst. Video Technol..