Milena Vratonjic

Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design

Bart R. Zeydel, Vojin G. Oklobdzija, Milena Vratonjic, 2006, PATMOS.

Power-aware circuit design and optimization for total chip power reduction

Milena Vratonjic, 2010 .

Low-power aspects of different adder topologies

Bart R. Zeydel, Vojin G. Oklobdzija, Milena Vratonjic, 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

The opportunity cost of low power design: a case study in circuit tuning

Matthew M. Ziegler, Victor V. Zyuban, George Gristede, 2009, ISLPED.

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

Vojin G. Oklobdzija, Matthew M. Ziegler, Thomas Mitchell, 2009, PATMOS.

Low- and ultra low-power arithmetic units: design and comparison

Bart R. Zeydel, Vojin G. Oklobdzija, Milena Vratonjic, 2005, 2005 International Conference on Computer Design.

Power and performance aware memory-controller voting mechanism

Gautam Kumar, Harmander Singh, Milena Vratonjic, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

Vojin G. Oklobdzija, Mandeep Singh, Christophe Giacomotto, 2008, PATMOS.