Shinichi Yasuda

发表

Detachable nano-carbon chip with ultra low power

H.-S. Philip Wong, Xiangyu Chen, Shinobu Fujita, 2010, Design Automation Conference.

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation

Kumiko Nomura, Shinobu Fujita, Keiko Abe, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

Flash-based nonvolatile programmable switch for low-power and high-speed FPGA by adjacent integration of MONOS/logic and novel programming scheme

Shinobu Fujita, Mari Matsumoto, Shinichi Yasuda, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs

Shinichi Yasuda, Masato Oda, Kosuke Tatsumura, 2014, International Conference on Field-Programmable Technology.

Perspectives and issues in 3D-IC from designers' point of view

Kumiko Nomura, Shinobu Fujita, Keiko Abe, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology pdf

Takao Marukame, Satoshi Takaya, Shinobu Fujita, 2017, ArXiv.

1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application

Shinobu Fujita, Tetsufumi Tanamoto, Mari Matsumoto, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

High-density user-programmable logic array based on adjacent integration of pure-CMOS crossbar antifuse into logic CMOS circuits

Mari Matsumoto, Shinichi Yasuda, Masato Oda, 2016, 2016 IEEE Symposium on VLSI Technology.

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only)

Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, 2010, FPGA '10.

Nonvolatile Programmable Switch With Adjacently Integrated Flash Memory and CMOS Logic for Low-Power and High-Speed FPGA

Mari Matsumoto, Shinichi Yasuda, Masato Oda, 2015, IEEE Transactions on Electron Devices.

Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection

Shinobu Fujita, Shinichi Yasuda, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Ultra Small Random Number Generating Circuits With A Novel Noise Source Device

Shinobu Fujita, Ken Uchida, Tetsufumi Tanamoto, 2003 .

Nonvolatile Configuration Memory Cell for Low Power Field Programmable Gate Array

Shinobu Fujita, Keiko Abe, Tetsufumi Tanamoto, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

Si nanocrystal MOSFET with silicon nitride tunnel insulator for high-rate random number generation

Daisuke Matsushita, Shinobu Fujita, Ken Uchida, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing

Yoshifumi Nishi, Tetsufumi Tanamoto, Shinichi Yasuda, 2018 .

Experimental Demonstration and Characterization of on-chip high speed graphene interconnects

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2010 .

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1 . 3 GHz Citation

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009 .

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

Shinobu Fujita, Shinichi Yasuda, H. Wong, 2008, Nano letters.

Non-stoichiometric SixN metal-oxide-semiconductor field-effect transistor for compact random number generator with 0.3 Mbit/s generation rate

Shinobu Fujita, Ken Uchida, Tetsufumi Tanamoto, 2008 .