Eiichi Teraoka

A built-in self-test for ADC and DAC in a single-chip speech CODEC

Narumi Sakashita, Takeshi Tokuda, Toru Kengaku, 1993, Proceedings of IEEE International Test Conference - (ITC).

A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC (Special Section on Analog Circuit Techniques for System-on-Chip Integration)

Takeshi Tokuda, Eiichi Teraoka, Ikuo Yasui, 1997 .

A 50 MHz 24 b floating-point DSP

Osamu Tomisawa, Toru Kengaku, Eiichi Teraoka, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A 1.8 V 36 mW DSP for the half-rate speech codec

Hisakazu Sato, Toru Kengaku, Eiichi Teraoka, 1996, Proceedings of Custom Integrated Circuits Conference.

Built-in self-test in a 24 bit floating point digital signal processor

Narumi Sakashita, Takeshi Tokuda, Toru Kengaku, 1990, Proceedings. International Test Conference 1990.

A 28 mW 16-bit Digital Signal Processor for the PDC Half-Rate CODEC (Special Issue on Low-Power LSI Technologies)

Takeshi Tokuda, Eiichi Teraoka, Kazuyuki Ishikawa, 1996 .