S. Bennett

A Reason to Add Registers

David Melski, S. Bennett, 1995 .

Very-Wide-Issue Superscalar Microengine Configurations

S. Bennett, 2007 .

Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching

James E. Smith, E. Rotenberg, S. Bennett, 1996, MICRO.

Trace cache: a low latency approach to high bandwidth instruction fetching

Eric Rotenberg, James E. Smith, Steve Bennett, 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

Evaluating Future Microprocessors: the SimpleScalar Tool Set

Doug Burger, Todd Austin, Steve Bennett, 1996 .

Control flow speculation in multiscalar processors

Quinn Jacobson, James E. Smith, Nikhil Sharma, 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

A Trace Cache Microarchitecture and Evaluation

Eric Rotenberg, James E. Smith, Steve Bennett, 1999, IEEE Trans. Computers.