C.L. Liu

Low Power Fpga Design - A Re-engineering Approach

Chau-Shen Chen, TingTing Hwang, C.L. Liu, 1997, Proceedings of the 34th Design Automation Conference.

Using Neural Networks to Solve VLSI Design Problems

Ran Libeskind-Hadas, C.L. Liu, R. Libeskind-Hadas, 1989, 1989 American Control Conference.

Fast search algorithms for reconfiguration problems

C.L. Liu, R. Libeskind-Hadas, R. Libeskind-Hadas, 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

Architecture driven circuit partitioning

C.L. Liu, C. L. Liu, Chau-Shen Chen, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

A performance-driven layer assignment algorithm for multiple interconnect trees

C.L. Liu, P. Saxena, Prashant Saxena, 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

Logic transformation for low power synthesis

Sung-Mo Kang, C.L. Liu, Ki-Wook Kim, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

C.L. Liu, Ki-Seok Chung, Ki-Seok Chung, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Noise-aware power optimization for on-chip interconnect

Sung-Mo Kang, Seong-Ook Jung, C.L. Liu, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

A fine-grained arithmetic optimization technique for high-performance flow-power data path synthesis

C.L. Liu, Junhyung Um, Thewhan Kim, 2000, Proceedings 37th Design Automation Conference.

Optimal clock period FPGA technology mapping for sequential circuits

C.L. Liu, Peichen Pan, P. Pan, 1996, 33rd Design Automation Conference Proceedings, 1996.