Hideki Kitada

发表

Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structures

Takayuki Ohba, Young-Suk Kim, Shigeaki Zaima, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis

Hiroko Tashiro, Tatsumi Nakada, Hideki Kitada, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

Development of ultra-thinning technology for logic and memory heterogeneous stack applications

Tadao Nakamura, K. Suzuki, Takayuki Ohba, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Direct Depth Measurement Tool of High Aspect Ratio Via-Hole for Three-Dimensional Stacked Devices (Proceedings of the 6th International Symposium on Practical Surface Analysis (PSA-13))

Makoto Nakamura, Hideki Kitada, Seiki Sakuyama, 2014 .

Development of high-performance ultra large scale 3D processor with high reliability packaging design

Naoaki Nakamura, Hideki Kitada, Aki Dote, 2017, 2017 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Development of high-yield and high-reliability design for high-performance ultra large scale 3DLSI processor

Hideki Kitada, 2017 .

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Koji Fujimoto, Takayuki Ohba, Tomoji Nakamura, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Influence of wafer thinning process on backside damage in 3D integration

Hiroshi Hashimoto, Tadao Nakamura, Takayuki Ohba, 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

Wafer-on-wafer (WOW) stacking with damascene-contact TSV for 3D integration

Takayuki Ohba, Hideki Kitada, Nobuhide Maeda, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

Takayuki Ohba, S. W. Kim, Hideki Kitada, 2012 .

Advanced wafer thinning technology and feasibility test for 3D integration

Young Suk Kim, Takayuki Ohba, Hideki Kitada, 2013 .

Development of multi-stack process on wafer-on-wafer (WOW)

Takayuki Ohba, Hideki Kitada, Nobuhide Maeda, 2010, 2010 IEEE CPMT Symposium Japan.

Height Dependent Resistivity of Copper Interconnects in the Size Effect

Takashi Suzuki, Hideki Kitada, Takahiro Kimura, 2007 .

Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction

Young Suk Kim, Takayuki Ohba, Shigeaki Zaima, 2011 .

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Naoto Horiguchi, Naoyoshi Tamura, Takayuki Ohba, 2003, IEEE International Electron Devices Meeting 2003.

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Yoshihiro Nakata, Takayuki Ohba, Hideki Kitada, 2011 .