Y. Mokhtari

Model Checking and Refinement of ASM Models Using SMV

Meral Shirazipour, S. Tahar, Y. Mokhtari, 2007 .

A Case Study on Model Checking and Refinement of Abstract State Machines

Meral Shirazipour, S. Tahar, Y. Mokhtari, 2001 .

Compositional Verification of a Switch Fabric from Nortel Networks

Sofiène Tahar, Hong Peng, Yassine Mokhtari, 2003, ICFEM.

A Path Dependency Graph for Verilog Program Analysis

Sofiène Tahar, Yassine Mokhtari, Mohamed Zaki, 2003 .

Validation of formal specifications

Dominique Méry, Yassine Mokhtari, D. Méry, 1999, AAAI 1999.

Animating TLA Specifications

Stephan Merz, Yassin Mokhtari, Stephan Merz, 1999, LPAR.

A New Approach for the Construction of Multiway Decision Graphs

Sofiène Tahar, Xiaoyu Song, Otmane Aït Mohamed, 2008, ICTAC.

SynAbs: model reduction tool for Verilog verification

Y. Mokhtari, S. Tahar, M. Zaki, 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..

SynAbs: model reduction tool for Verilog verification

S. Tahar, Y. Mokhtari, Mohamed H. Zaki, 2004 .

Animating formal specifications : a telephone simulation case study

Dominique Méry, John Paul Gibson, Yassine Mokhtari, 1999 .