Clement Tavernier

发表

Experimental and numerical investigations on Cu/low-k interconnect reliability during copper pillar shear test

Vincent Fiori, Sebastien Gallois-Garreignot, Clement Sart, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops

Philippe Roche, Gilles Gasiot, Jean-Luc Autran, 2009, 2009 European Conference on Radiation and Its Effects on Components and Systems.

Chip Package Interactions: Package effects on copper pillar bump induced BEoL delaminations & associated numerical developments

Guojun Hu, Vincent Fiori, Sebastien Gallois-Garreignot, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

Characterization and modelling of gate current injection in embedded non-volatile flash memory

Yusuf Leblebici, Alban Zaka, Pierpaolo Palestri, 2011, 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

Dynamic Charge Sharing modeling for surface potential based models

Clement Tavernier, Denis Rideau, Raphael Clerc, 2009 .

Embedded non–volatile memory study with surface potential based model

Yusuf Leblebici, Alban Zaka, M. Minondo, 2009 .

Technology Computer Aided Design of 65nm SOI MOSFETs through Integrated Process and Device Simulations

E. M. Bazizi, Clement Tavernier, A. Pakfar, 2010 .

Packaging induced stress effects investigations on 40nm CMOS technology node: Measurements and optimization of device shifts

Pierre-Olivier Bouchard, Vincent Fiori, Sebastien Gallois-Garreignot, 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).

Advanced physics for simulation of ultrascaled devices with UTOXPP solver

Yusuf Leblebici, Alexandre Schmid, Clement Tavernier, 2011 .

Modeling of the effect of the buried Si–SiO2 interface on transient enhanced boron diffusion in silicon on insulator

H. Kheyrandish, E. M. Bazizi, Clement Tavernier, 2010 .

Modeling study of capacitance and gate current in strained HighK-Metal gate technology

Yusuf Leblebici, Alexandre Schmid, Clement Tavernier, 2010 .

Modeling of Electromigration Induced Failure Mechanism in Semiconductor Devices

Florian Cacho, Clement Tavernier, Herve Jaouen, 2007 .

Investigations of Thermomechanical Stress Induced by TSV-Middle (Through-Silicon via) in 3-D ICs by Means of CMOS Sensors and Finite-Element Method

Pierre-Olivier Bouchard, Vincent Fiori, Sebastien Gallois-Garreignot, 2015, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Modeled optical properties of SiGe and Si layers compared to spectroscopic ellipsometry measurements

Christophe Delerue, Clement Tavernier, Denis Rideau, 2017 .

Experimental investigations and simulation of the deactivation of arsenic during thermal processes after activation by SPER and spike annealing

H. Kheyrandish, Clement Tavernier, Peter Pichler, 2008 .

Modeling study of capacitance and gate current in strained High–K Metal gate technology: impact of Si/SiO2/HK interfacial layer and band structure model

Yusuf Leblebici, Alexandre Schmid, Clement Tavernier, 2010 .