H. Asai

发表

Neural network simulator for spatiotemporal pattern analysis

A. Kamo, H. Ninomiya, Teru Yoneyama, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

An Application of Analog Behavioral Description by C/C++ Language to ASSIST

H. Asai, Akinobu Nishio, Takayuki Watanabe, 1999 .

A synthesis technique of time-domain interconnect models by MIMO type of adaptive least square method

A. Kamo, H. Asai, Masaya Suzuki, 2000, IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524).

A stabilized leapfrog scheme for circuit-based analysis of power delivery network

Tadatoshi Sekine, H. Asai, 2016 .

Synthesis of time-domain models for interconnects having 3-D structure based on FDTD method

H. Asai, Takayuki Watanabe, 2000 .

Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique

A. Kamo, H. Asai, H. Kubota, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Efficient Electromagnetic Simulation Including Thin Structures by Using Multi-GPU HIE-FDTD Method

Atef Z. Elsherbeni, Payam Nayeri, H. Asai, 2016 .

Fast transient analysis of power distribution network modeled by unstructured meshes by using locally implicit latency insertion method

H. Asai, S. Okada, H. Kurobe, 2012, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation

H. Asai, Y. Tanji, A. Tsuzaki, 2007, 2007 18th European Conference on Circuit Theory and Design.

An alternating implicit block overlapped FDTD (AIBO-FDTD) method and its estimation with parallel computation

A. Kamo, H. Asai, P. Pongpaibool, 2001, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565).

An Application of Modeling with an Analog Hardware Description Language to ASSIST

H. Asai, Hiroshi Sagesaka, Hisashi Irii, 1997 .

A New Methodology for Optimal Placement of Decoupling Capacitors on Printed Circuit Board

A. Kamo, H. Asai, Takayuki Watanabe, 2001 .

Unified circuit modeling technique for the simulation of electrostatic discharge (ESD) injected by an ESD generator

H. Asai, T. Sekine, J. S. Lee, 2012, 2012 IEEE International Symposium on Electromagnetic Compatibility.

Mixed Signal Simulator SPLIT3 with Analog/Digital Mixed Circuit Emphasis

H. Asai, Hisashi Irii, 1997 .

An approach for reducing common-mode current on electronic control units using optimization algorithm

H. Asai, T. Unou, K. Shinomiya, 2008, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility.

Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique

H. Asai, T. Watanabe, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Modeling and simulation of phase-locked loop with Verilog-A description for top-down design

H. Asai, Y. Hiraku, T. Oura, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Nonlinear block-type leapfrog scheme for the fast simulation of multiconductor transmission lines with nonlinear drivers and terminations

H. Asai, T. Sekine, 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

AVAILABILITY OF VIRTUAL STATE RELAXATION TECHNIQUE IN TIMING ANALYSIS

H. Asai, Yasuozi Tanaka, 1989 .

Alternating Direction Explicit-Latency Insertion Method (ADE-LIM) for the Fast Transient Simulation of Transmission Lines

H. Asai, H. Kurobe, T. Sekine, 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Multi-Rate FDTD Method for Fast Electromagnetic Simulation

H. Asai, Y. Nakazono, 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

AHDL-Oriented Circuit Simulator for Analog / Digital Mixed Circuits

Masakatsu Nishigaki, H. Asai, Shingo Fujimori, 1995 .

A synthesis technique of time-domain interconnect models by MIMO type of selective orthogonal least-square method

A. Kamo, H. Asai, Takayuki Watanabe, 2001 .

CMOS circuit simulation using Latency Insertion Method

Tadatoshi Sekine, H. Asai, 2008 .

DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits

H. Asai, T. Watanabe, 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

Multi-Rate Latency insertion Method for the Fast Transient Simulation of Large Networks with Nonlinear Termination

H. Asai, N. Tsuboi, 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

Application of neuro-based optimization algorithm to three dimensional cylindric puzzles

H. Asai, Hiroyuki Yamamoto, Hiroshi Ninomiya, 1997, Proceedings of International Conference on Neural Networks (ICNN'97).

SOM-LS: selective orthogonal matrix least-squares method for macromodeling multiport networks characterized by sampled data

H. Asai, Y. Tanji, T. Watanabe, 2003, Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation.

Improvement of discrete-time cellular neural networks for associative memory using 2-dimensional discrete Walsh transform

H. Asai, T. Kamio, 1998, 1998 Fifth IEEE International Workshop on Cellular Neural Networks and their Applications. Proceedings (Cat. No.98TH8359).

Waveform relaxation algorithm with virtual state formulation technique and its multirate behavior

H. Asai, K. Hayashi, 1991, China., 1991 International Conference on Circuits and Systems.

Parallel-Distributed Block-LIM for Transient Simulation of Tightly Coupled Transmission Lines

H. Asai, T. Sekine, Y. Inoue, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

An efficient learning algorithm with second-order convergence for multilayer neural networks

H. Asai, Hiroshi Ninomiya, C. Tomita, 2003, Proceedings of the International Joint Conference on Neural Networks, 2003..

Efficient generation of reduced-order interconnect macromodels using RLCG MNA formulation

H. Asai, T. Watanabe, Y. Tanji, 2005, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005..

Trend of Circuit Simulation Based on Electromagnetic Field Analysis and Model Order Reduction Techniques

H. Asai, 2001 .

VIRTUAL STATE RELAXATION TECHNIQUE FOR CIRCUIT SIMULATION AND ITS PROPERTIES

H. Asai, Takeshi Kokado, 1988 .

Fast fullwave simulation based on parallel-distributed HIE-FDTD method

H. Asai, Y. Inoue, H. Asai, 2012, 2012 Asia Pacific Microwave Conference Proceedings.

Circuit/Electromagnetic hybrid simulation of electrostatic discharge in contact discharge mode

H. Asai, T. Sekine, T. Takada, 2012, International Symposium on Electromagnetic Compatibility - EMC EUROPE.

Multi-Rate Latency Insertion Method with RLCG-MNA Formulation for Fast Transient Simulation of Large-Scale Interconnect and Plane Networks

H. Asai, N. Tsuboi, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

SPADE : analog/digital mixed signal simulator with analog hardware description language

H. Asai, Hisashi Irii, H. Sagesaka, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Optimization procedure of class E amplifiers using SPICE

H. Asai, H. Sekiya, Y. Tanji, 2005, Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005..

An efficient learning algorithm for finding multiple solutions based on fixed-point homotopy method

H. Asai, H. Ninomiya, C. Tomita, 2005, Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005..

Analysis of power/ground planes by PCB simulator with model order reduction technique

A. Kamo, H. Asai, H. Kubota, 2001, IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565).

An explicit and unconditionally stable finite difference scheme for the fast transient analysis of a power distribution network

H. Asai, T. Sekine, N. Nishizaki, 2012, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

Neural network approach to traveling salesman problem based on hierarchical city adjacency

H. Ninomiya, H. Asai, Takeshi Nakayama, 1995, Proceedings of ICNN'95 - International Conference on Neural Networks.

Design of 3-valued neural networks with cyclic connection for limit cycle generator

Teru Yoneyama, H. Asai, Hiroshi Ninomiya, 1998, 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227).

HIE-FDTD Method for Hybrid System With Lumped Elements and Conductive Media

H. Asai, H. Asai, M. Unno, 2011, IEEE Microwave and Wireless Components Letters.

Transient simulation of multilayered power distribution network based on block-type alternating direction implicit scheme

H. Asai, T. Sekine, T. Ishimaru, 2012, 2012 Asia-Pacific Symposium on Electromagnetic Compatibility.

Mixed finite element time domain method based on iterative leapfrog scheme for fast simulations of electromagnetic problems

H. Asai, T. Sekine, H. Asai, 2011, 2011 IEEE International Symposium on Electromagnetic Compatibility.

Application of neuro-based optimization to 3-D rectangular puzzles

H. Asai, Hiroshi Ninomiya, Hiroyuki Yamamoto, 1998, 1998 IEEE International Joint Conference on Neural Networks Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36227).

Locally Implicit LIM for the Simulation of PDN Modeled by Triangular Meshes

H. Asai, H. Kurobe, T. Sekine, 2012, IEEE Microwave and Wireless Components Letters.