Hiroshima Yu

Ｄesign Method of system LSI with FinFET type DTMOS

Watanabe Shigeyoshi, Hiroshima Yu, Okamoto Keisuke, 2007 .

New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI

Hiroshima Yu, Okamoto Keisuke, Koizumi Keisuke, 2008 .

Study of pattern area reduction with 3 dimensional transistor for logic circuit

Watanabe Shigeyoshi, Kodama Takahiro, Hiroshima Yu, 2011 .

Reducing pattern area technology of 3D transistor for system LSI

Watanabe Shigeyoshi, Hiroshima Yu, 2009 .

New design technology of independent-gate controlled Double-Gate transistor for LSI

Watanabe Shigeyoshi, Hiroshima Yu, Okamoto Keisuke, 2008 .