Weitao Pan

Dual priority congestion aware shared-resource Network-on-Chip architecture

Huaxi Gu, Peijun Ma, Jiangyi Shi, 2016, IEICE Electron. Express.

Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

Z. Qiu, Weitao Pan, Ling Zheng, 2020 .

An Efficient Framework with Node Filtering and Load Expansion for Machine-Learning-Based Hardware Trojan Detection

Z. Qiu, Weitao Pan, Ling Zheng, 2022, Electronics.

Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches

Ling Zheng, Dong Zhang, Zhiliang Qiu, 2018, 2018 International Conference on Computer, Information and Telecommunication Systems (CITS).

Access mechanism for period flows of non-deterministic end systems for time-sensitive networks

Z. Qiu, Weitao Pan, Ling Zheng, 2023, Computer Networks.

Eventor

Bei Yu, Jianlei Yang, Weitao Pan, 2022, Proceedings of the 59th ACM/IEEE Design Automation Conference.

Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform

Weisheng Zhao, Bei Yu, Weitao Pan, 2022, DAC.

A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection

Huan Liu, Z. Qiu, Weitao Pan, 2022, IEEE Access.

A unioned graph neural network based hardware Trojan node detection

Z. Qiu, Zhixiong Di, Weitao Pan, 2023, IEICE Electron. Express.

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation

Weina Wang, Zhiliang Qiu, Ya Gao, 2019, J. Circuits Syst. Comput..