Kazuhiko Iwasaki

发表

A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR DETECTION CAPABILITY

Yuji Sato, Marius V. A. Hâncu, Kazuhiko Iwasaki, 1991, 1991, Proceedings. International Test Conference.

Reduction of Area per Good Die for SoC Memory Built-In Self-Test

Masayuki Arai, Kazuhiko Iwasaki, Tatsuro Endo, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Evaluation of convolutional-code-based FEC under limited recovery time and its application to real-time transmission

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2002, 2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings..

On the maximum value of aliasing probabilities for single input signature registers

Tadao Kasami, Toru Fujiwara, Kazuhiko Iwasaki, 1993, VTS.

Analysis of using convolutional codes to recover packet losses over burst erasure channels

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2001, Proceedings 2001 Pacific Rim International Symposium on Dependable Computing.

Hybrid BIST using partially rotational scan

Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara, 2001, Proceedings 10th Asian Test Symposium.

2009 27th IEEE VLSI Test Symposium

Masayuki Arai, Bernd Becker, Kazumi Hatayama, 2009 .

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)

Satoshi Fukumoto, Kazumi Hatayama, Kazuhiko Iwasaki, 2002 .

BIST Pattern Generator for Detection of Delay Faults

Kazuhiko Iwasaki, Seiji Kajihara, Takeshi Asakawa, 2000 .

Hardware Overhead Reduction for Memory BIST

Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, 2008, 2008 IEEE International Test Conference.

Method to recover lost Internet packets using (n, k, m) convolutional codes

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2005 .

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development

Masayuki Arai, Masayuki Sato, Kazuhiko Iwasaki, 2008, J. Inf. Process. Syst..

Note on Fast Bridge Fault Test Generation Based on Critical Area

Masayuki Arai, Kazuhiko Iwasaki, Shingo Inuyama, 2015, ICA3PP.

Analysis of error-masking and X-masking probabilities for convolutional compactors

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2005, IEEE International Conference on Test, 2005..

A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

Finding a recovery line in uncoordinated checkpointing

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2004, 24th International Conference on Distributed Computing Systems Workshops, 2004. Proceedings..

Application of Coding Theory to Computer Systems, Control Theory and Digital Signal Processing Algorithms

Kazuhiko Iwasaki, Masakatu Morii, 1994 .

Seed selection procedure for LFSR-based BIST with multiple scan chains and phase shifters

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2004, 13th Asian Test Symposium.

Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors

Masayuki Arai, Kazuhiko Iwasaki, 2011, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing.

Study on Expansion of Convolutional Compactors over Galois Field

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2008, IEICE Trans. Inf. Syst..

Aliasing error for a mask ROM built-in self-test

Kazuhiko Iwasaki, Shigeo Nakamura, Akinori Furuta, 1994, Proceedings of IEEE VLSI Test Symposium.

Aliasing Probabilities and Weight Distributions of Several Codes

Kazuhiko Iwasaki, Tadahiko Nishimukai, 1989, Systems and Computers in Japan.

On the maximum value of aliasing probabilities for single input signature registers

Tadao Kasami, Toru Fujiwara, Kazuhiko Iwasaki, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Decoding method for shortened fire codes and its application to VLSI processor

Kazuhiko Iwasaki, Tsuneo Funabashi, Tatsuaki Ueno, 1987, Systems and Computers in Japan.

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2008, IEICE Trans. Inf. Syst..

Analysis of probabilistic trapezoid protocol for data replication

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

Deterministic Built-in Test for Logic Circuits Having Multiple Clocks

Satoshi Fukumoto, Kazumi Hatayama, Kazuhiko Iwasaki, 2003 .

A Simulation of Parallel Machines Using N.2 Architecture Simulator

Kazuhiko Iwasaki, Satoshi Ishii, 1993 .

Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing

Kazuhiko Iwasaki, 1990, Systems and Computers in Japan.

Stochastic and statistical analyses of the distribution of fault coverage in random-pattern testing

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2010, 2010 10th International Symposium on Communications and Information Technologies.

Study on Test Data Reduction Combining Illinois Scan and Bit Flipping

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2008, IEICE Trans. Inf. Syst..

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test

Masayuki Arai, Brion L. Keller, Kazuhiko Iwasaki, 2009, J. Low Power Electron..

A proposal and evaluation of a coordinated checkpointing technique using incremental snapshots

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2007 .

Chapter 11: Hybrid Coordinated Checkpointing Technique Using Incremental Snapshots

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2014 .

Evaluation of multicast error recovery using convolutional codes

Masayuki Arai, Kazuhiko Iwasaki, Anna Yamaguchi, 2000, Proceedings. 2000 Pacific Rim International Symposium on Dependable Computing.

Small Delay Fault Model for Intra-Gate Resistive Open Defects

Masayuki Arai, Kazumi Hatayama, Kazuhiko Iwasaki, 2009, 2009 27th IEEE VLSI Test Symposium.

Analytical Evaluation of Internet Packet Loss Recovery Using Convolutional Codes

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2002 .

Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering

Masayuki Arai, Kazuhiko Iwasaki, Shingo Inuyama, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2013, IEICE Trans. Inf. Syst..

Session 6C — IP Session: Test Strategies of Leading Edge SoCs

Satoshi Fukumoto, Kazumi Hatayama, Kazuhiko Iwasaki, 2006 .

C-24 Implementation and Experiments on Dependable Video Conference System

Hee Yong Youn, Masayuki Arai, Satoshi Fukumoto, 2002 .

A uniform network for VLSI massively parallel computers

Yuji Sato, Kazuhiko Iwasaki, Christian Iseli, 1993, Systems and Computers in Japan.

Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration

Masahiro Takakura, Kazuhiko Iwasaki, Yasuo Sato, 2004, IEICE Trans. Inf. Syst..

Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor

Kazuhiko Iwasaki, Ikuya Kawasaki, Tadahiko Nishimukai, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

A seed selection procedure for LFSR-based random pattern generators

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2003, ASP-DAC '03.

Using ATPG vectors for BIST test pattern generator

Kazuhiko Iwasaki, Takeshi Asakawa, 2001, Systems and Computers in Japan.

Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit

Kazuhiko Iwasaki, Noboru Yamaguchi, Yoshimune Hagiwara, 1986, Systems and Computers in Japan.

Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage

Masayuki Arai, Kazuhiko Iwasaki, Yoshihiro Shimizu, 2012, 2012 IEEE 21st Asian Test Symposium.

BIST-oriented test pattern generator for detection of transition faults

Kazuhiko Iwasaki, Seiji Kajihara, Takeshi Asakawa, 2003, Systems and Computers in Japan.

IMPLEMENTATION OF XCAST FOR HIGH-RELIABLE TV CONFERENCE SYSTEM

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2002 .

Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation

Masayuki Arai, Kazuhiko Iwasaki, Shingo Inuyama, 2017, 2017 IEEE International Test Conference (ITC).

Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2006, Comput. Math. Appl..

Design of signature circuits based on weight distributions of error-correcting codes

Kazuhiko Iwasaki, Noboru Yamaguchi, 1990, Proceedings. International Test Conference 1990.

A defect-tolerant design for mask ROMs

Tadao Kasami, Toru Fujiwara, Kazuhiko Iwasaki, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Analysis of read and write availability for generalized hybrid data replication protocol

Hee Yong Youn, Masayuki Arai, Satoshi Fukumoto, 2004, 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings..

Measurement and modeling of burst packet losses in Internet end-to-end communications

Masayuki Arai, Kazuhiko Iwasaki, Atsushi Chiba, 1999, Proceedings 1999 Pacific Rim International Symposium on Dependable Computing.

Test Data Compression of 100x for Scan-Based BIST

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2006, 2006 IEEE International Test Conference.

Classification of DNS Queries for Anomaly Detection

Kazuhiko Iwasaki, Hongbo Shi, 2013, 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing.

C-023 Evluation of Stuck-at Fault Tolerance of TMR Processor by Using Fault Injections

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2007 .

Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers

Yuji Sato, Marius V. A. Hâncu, Kazuhiko Iwasaki, 1992, Parallel Comput..

Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2004, IEICE Trans. Inf. Syst..

Critical-Area-Aware Test Pattern Generation and Reordering

Masayuki Arai, Kazuhiko Iwasaki, Shingo Inuyama, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

A Study of Burst Packet Loss Recovery Using Convolutional Codes

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2001 .

Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage

Masayuki Arai, Kazuhiko Iwasaki, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analysis of Probabilistic Trapezoid Protocol for Data Replication

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2008, J. Inf. Process..

Iiasling Error for a Mask RO Built-In Self-Test

Kazuhiko Iwasaki, Shigeo Nakamura, 1996 .

Implementation of memory tester consisting of SRAM-based reconfigurable cells

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2003, 2003 Test Symposium.

BIST Oriented TPG for n-Detection Test

Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara, 2000 .

CMOS hard disk controller with data buffer and error correction

Kazuhiko Iwasaki, T. Funabashi, J. Tatezaki, 1984 .

Adaptive checkpointing for time warp technique with a limited number of checkpoints

Satoshi Fukumoto, Kazuhiko Iwasaki, Ryo Suzuki, 2002, Proceedings 22nd International Conference on Distributed Computing Systems Workshops.

Outline of Gmicro/200 and Memory Management Mechanism

Kazuhiko Iwasaki, Ikuya Kawasaki, Tadahiko Nishimukai, 1987 .

A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability

Yuji Sato, Marius V. A. Hâncu, Kazuhiko Iwasaki, 1994, IEEE Trans. Parallel Distributed Syst..

Method to recover Internet packet losses using (n, n-1, m) convolutional codes

Masayuki Arai, Kazuhiko Iwasaki, Anna Yamaguchi, 2000, Proceeding International Conference on Dependable Systems and Networks. DSN 2000.

Mesh Spiral and Mesh Random Networks (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)

Kazuhiko Iwasaki, Akinori Furuta, 1996 .

A Note on Aliasing Probability for Multiple Input Signature Analyzer

Kazuhiko Iwasaki, Masakatu Morii, 1993, IEEE Trans. Computers.

A CONCURRENT TEST ARCHITECTURE AND ITS ERROR DETECTION CAPABILITY FOR MASSIVELY-PARALLEL COMPUTERS

Kazuhiko Iwasaki, Mamoru Sugie, Marius V. A. Hancu, 1991 .

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression

Masayuki Arai, Brian Foutz, Brion L. Keller, 2010, IEICE Trans. Inf. Syst..

Fault Analysis in Mask ROM and its Application to Signature Circuit Design

Kazuhiko Iwasaki, Shigeo Nakamura, Akinori Furuta, 1994 .

Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks

Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions

Tadao Kasami, Prawat Nagvajara, Kazuhiko Iwasaki, 1995 .