R.K. Krishnamurthy

发表

A process variation compensating technique for sub-90 nm dynamic circuits

A. Alvandpour, C.H. Kim, K. Roy, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits

A. Alvandpour, V. De, S. Borkar, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

B. Bloechel, S. Borkar, R.K. Krishnamurthy, 2004, IEEE Journal of Solid-State Circuits.

Dual supply voltage clocking for 5 GHz 130 nm integer execution core

M. Sachdev, B. Bloechel, S. Borkar, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

High-performance interconnect design for systems-on-chip

Shih-Lien Lu, K. Soumyanath, R.K. Krishnamurthy, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS

A. Agarwal, R.K. Krishnamurthy, N. Banerjee, 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

A 4.5 GHz 130 nm 32 KB L0 cache with a self reverse bias scheme

A. Alvandpour, S. Borkar, S. Mathew, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

S. Borkar, R.K. Krishnamurthy, S.K. Mathew, 2008, IEEE Journal of Solid-State Circuits.

High-performance and low-voltage challenges for sub-45nm microprocessor circuits

S. Borkar, R.K. Krishnamurthy, S.K. Mathew, 2005, 2005 6th International Conference on ASIC.

On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations

C.H. Kim, K. Roy, S. Borkar, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors

A. Alvandpour, S. Borkar, R.K. Krishnamurthy, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

A. Alvandpour, M. Sachdev, S. Borkar, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

S. Borkar, R.K. Krishnamurthy, S.K. Mathew, 2009, IEEE Journal of Solid-State Circuits.

A low-swing single-ended L1 cache bus technique for sub-90nm technologies

S. Borkar, R.K. Krishnamurthy, M.A. Anders, 2004, Proceedings of the 30th European Solid-State Circuits Conference.

An on-die CMOS leakage current sensor for measuring process variation in sub-90nm generations

C.H. Kim, S. Borkar, S. Hsu, 2004, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

A 90nm 6.5GHz 128/spl times/64b 4-read 4-write ported parameter variation tolerant register file

K. Roy, S. Borkar, S. Hsu, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A 9GHz 320×80bit Low Leakage Microcode Read Only Memory in 65nm CMOS

A. Alvandpour, A. Agarwal, R.K. Krishnamurthy, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A Dual-Supply 4GHz 13fJ/bit/search 64×128b CAM in 65nm CMOS

Himanshu Kaul, A. Agarwal, R.K. Krishnamurthy, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit

R.K. Krishnamurthy, S.K. Mathew, M.A. Anders, 2006, IEEE Journal of Solid-State Circuits.