V. Nguyen

Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition

Duc Minh Nguyen, Han Le Duc, Olivier Jamin, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Advantages of high-pass ?S modulators in interleaved ?S analog to digital converter

Van Tam Nguyen, Patrick Loumeau, J.-F. Naviner, 2002 .

Correction analog defects in analog / digital parallel, in particular for multi-standard applications, software radio and / or cognitive radio.

Van Tam Nguyen, Patrick Loumeau, Ali Beydoun, 2009 .

A 1 V 65 nm CMOS Reconfigurable Time Interleaved High Pass SigmaDelta ADC.

Van Tam Nguyen, Patrick Loumeau, Chadi Jabbour, 2009, ISCAS 2009.

A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass ΔΣ Modulators.

Van Tam Nguyen, Patrick Loumeau, Hasham Ahmed Khushk, 2011 .

A fully digital background calibration of timing skew in undersampling TI-ADC

Han Le Duc, Olivier Jamin, Patricia Desgreys, 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

Estimation techniques for timing mismatch in time-interleaved analog-to-digital converters: Limitations and solutions

Han Le Duc, Patricia Desgreys, Van Tam Nguyen, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A low-power ΣΔ ADC optimized for GSM/EDGE standard in 65-nm CMOS

Van Tam Nguyen, Patrick Loumeau, Chadi Jabbour, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).