C. Verove

Integration of Fluorine-doped Silicon oxide in copper pilot line for 0.12-µm technology

K. Barla, J. Michailos, C. Chaton, 2002 .

Impact of ambient atmosphere on plasma-damaged porous low-k characterization

N. Possémé, T. Chevolleau, N. Rochat, 2011, 2011 IEEE International Interconnect Technology Conference.

Residue growth on metallic hard mask after dielectric etching in fluorocarbon based plasmas. II. Solutions

P. Brun, N. Possémé, T. Chevolleau, 2010 .

Scatterometric Porosimetry for porous low-k patterns characterization

N. Possémé, T. Chevolleau, C. Licitra, 2011, 2011 IEEE International Interconnect Technology Conference.

Integration of a 3 level Cu-SiO/sub 2/ air gap interconnect for sub 0.1 micron CMOS technologies

M. Guillermet, P. Gayet, R. Gonella, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Plasma treatments to improve line-width roughness during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Unbiased line width roughness measurements with critical dimension scanning electron microscopy and critical dimension atomic force microscopy

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2012 .

Electron-shading characterization in a HDP contact etching process using a patterned CHARM wafer

G. Reimbold, M. Haond, W. Lukaszek, 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).