K. T. Lau

Simplified architecture of a fuzzy inference processor

M. H. Lim, J. S. Ho, K. T. Lau, 1993, Proceedings 1993 The First New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems.

An Adiabatic 4: 2 Compressor Design for Low Power VLSI

K. T. Lau, K. W. Ng, 1999, J. Circuits Syst. Comput..

Dual‐rail improved adiabatic pseudo‐domino logic with auxiliary clock: a low‐power partially‐adiabatic CMOS logic family

K. T. Lau, W. M. Tan, 2003 .

A NOVEL ADIABATIC REGISTER FILE DESIGN

K. T. Lau, K. W. Ng, 2000 .

A Novel Adiabatic Register File Design

K. W. Ng, K. T. Lau, 2000, J. Circuits Syst. Comput..

Energy‐recovery low power C‐PAL flip‐flop design

K. T. Lau, H. H. Wong, 2001 .

Design and implementation of an FPGA transponder

K. T. Lau, S. C. Mar, B. H. Tan, 1995, Microprocess. Microsystems.

Low Power Adiabatic Programmable Logic Array with Single Clock Iapdl

Y. Zhou, K. T. Lau, W. J. Yang, 2008, J. Circuits Syst. Comput..

A microprocessor-based gate security system

K. T. Lau, Y. K. Choo, 1989 .

Improved Dynamic Current Mode Logic for Low Power Applications

S. Ramakrishnan, K. T. Lau, 2008, J. Circuits Syst. Comput..

Programmable digital neuron using pulsewidth-coded data

K. T. Lau, S. H. Kang, Y. K. Choo, 1998, Microprocess. Microsystems.