Jihyuck Jo

Encoder Using Two-dimensional Encoding Scheme

In-Cheol Park, Jihyuck Jo, Youngjoo Lee, 2013 .

Low-Latency Low-Cost Architecture for Square and Cube Roots

In-Cheol Park, Jihyuck Jo, I. Park, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Modified Viterbi Scoring for HMM-based Speech Recognition

Bang Chul Jung, Jihyuck Jo, Hoyoung Yoo, 2019, Intelligent Automation and Soft Computing.

Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow

Jihyuck Jo, In-Cheol Park, Suchang Kim, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks

Jihyuck Jo, Soyoung Cha, In-Cheol Park, 2018, IEEE Journal of Solid-State Circuits.

Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing

In-Cheol Park, Jihyuck Jo, Suchang Kim, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

In-Cheol Park, Byeong Yong Kong, Jihyuck Jo, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

In-Cheol Park, Jihyuck Jo, Youngjoo Lee, 2013, IEEE Journal of Solid-State Circuits.

SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads

Liangzhen Lai, V. Chandra, Jinook Song, 2022, ArXiv.

Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems

In-Cheol Park, Jihyuck Jo, Hoyoung Yoo, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.