Ashok K. Saxena

发表

Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach

Balwinder Raj, Sudeb Dasgupta, Ashok K. Saxena, 2011, SocProS.

Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2011, IET Circuits Devices Syst..

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Bulusu Anand, Archana Pandey, Sudeb Dasgupta, 2014, IEEE Transactions on Electron Devices.

Radiation Effects in MOS-based Devices and Circuits: A Review

Sudeb Dasgupta, S. S. Rathod, Ashok K. Saxena, 2011 .

Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study

Sudeb Dasgupta, Ashok K. Saxena, D. Sreenu, 2009, J. Low Power Electron..

Application of Feedback Switch Logic for the Design of Low Power High Speed ALU

Ashok K. Saxena, Patanjali Prakash, 2009 .

Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2010, J. Low Power Electron..

Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2011, Microelectron. J..

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2016, Microelectron. J..

Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2012, VDAT.

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2010, Microelectron. Reliab..

Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2012, IET Circuits Devices Syst..

Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology

Balwinder Raj, Sudeb Dasgupta, Ashok K. Saxena, 2011, J. Low Power Electron..

Design of Low Power High Speed ALU Using Feedback Switch Logic

Ashok K. Saxena, Patanjali Prakash, 2009, 2009 International Conference on Advances in Recent Technologies in Communication and Computing.

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

Sudeb Dasgupta, Ashok K. Saxena, Surendra S. Rathod, 2011, Microelectron. Reliab..

Impact of dual-k spacer on analog performance of underlap FinFET

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2012, Microelectron. J..

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach

Balwinder Raj, Sudeb Dasgupta, Ashok K. Saxena, 2010, 2010 Fourth UKSim European Symposium on Computer Modeling and Simulation.

Analytical Modeling of Inversion Charge Density for Nanoscale Dual Metal Gate (Hf/AlN x ) and Midgap Symmetric Double Gate MOSFET

Sudeb Dasgupta, Ashok K. Saxena, S. K. Vishvakarma, 2010 .

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2013, IEEE Transactions on Electron Devices.

The conduction band structure and deep levels in Ga1-xAlxAs alloys from a high-pressure experiment

Ashok K. Saxena, A. Saxena, 1980 .

Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device

Sudeb Dasgupta, S. S. Rathod, Ashok K. Saxena, 2011 .

Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Sudeb Dasgupta, Ashok K. Saxena, Ashutosh Nandi, 2014, IEEE Transactions on Electron Devices.