Sanghyun Ku

Sequential Paging under Delay Bound for Next Generation Mobile Systems

Chae Y. Lee, Sanghyun Ku, 2006 .

A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement

Sangil Park, Jonghwan Kim, K. Jang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme

Hankyu Chi, Dongkyun Kim, Changhyun Lee, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Dongkyun Kim, Minsu Park, Mingyu Park, 2020, IEEE Journal of Solid-State Circuits.