Joo-Sun Choi

发表

A fast path-based method for 3-D resist development simulation

Byeong-soo Kim, Soo-Young Lee, Q. Dai, 2014 .

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

Young-Hyun Jun, Kee-Won Kwon, Su-Jin Park, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park, 2010, IEEE Custom Integrated Circuits Conference 2010.

Antifuse EPROM circuit for field programmable DRAM

Jae-Kyung Wee, Jin-Yong Chung, Chang-Hyuk Lee, 2000 .

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Jung-Hwan Choi, Min-Ho Park, Kwang-Il Park, 2013, 2013 Symposium on VLSI Circuits.

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface

Jae-Yoon Sim, Hong-June Park, Young-Sik Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

F1: Silicon 3D-integration technology and systems

Vladimir Stojanovic, Hideto Hidaka, Ken Takeuchi, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Jung-Bae Lee, Sang-Hoon Jung, Kyungseok Oh, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

Young-Hyun Jun, Lee-Sup Kim, Kinam Kim, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

5.7 A 29nW bandgap reference circuit

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An effective routing methodology in the era of 0.2 /spl mu/m and beyond technologies for reducing the DRAM design cost

Jae-Kyung Wee, Jong Woo Kim, Chang-Hyuk Lee, 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

WP 24.8 Antifuse EPROM Circuit for Field Programmable DRAM

Jae-Kyung Wee, Jin-Yong Chung, Chang-Hyuk Lee, 2000 .

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

Young-Hyun Jun, Jeong-Don Ihm, Bai-Sun Kong, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme

Lee-Sup Kim, Young-Ju Kim, Seung-Jun Bae, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2011, IEICE Trans. Electron..

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

Young-Hyun Jun, Lee-Sup Kim, Kwang-Il Park, 2009, IEEE J. Solid State Circuits.

Charge recycling differential logic (CRDL) for low power application

Kwyro Lee, Seog-Jun Lee, Bai-Sun Kong, 1996 .

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Jung-Hwan Choi, Seok-Ho Lee, Hundai Choi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking

Young-Hyun Jun, Byongwook Na, Donghyuk Lee, 2011, IEEE Journal of Solid-State Circuits.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Simple Formulas for Interconnect Delay and Crosstalk Considering the Transition Time of Ramp Signals

Jae-Kyung Wee, Chang-Hyuk Lee, Seong-Hoon Lee, 1999 .

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Young Choi, Jung-Hwan Choi, Jongeun Lee, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

Young-Hyun Jun, Byongwook Na, Donghyuk Lee, 2011, 2011 IEEE International Solid-State Circuits Conference.

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

O Seongil, Jung Ho Ahn, Nam Sung Kim, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module

Jun-Dong Cho, Joo-Sun Choi, Woo-Seop Kim, 2013, 2013 IEEE International SOC Conference.

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Sung Kyu Lim, Yarui Peng, Bon Woong Ku, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.

FPGA-based DDR3 DRAM interface using bulk-Si optical interconnects

Dong-Jae Shin, Chilhee Chung, Ho-Cheol Lee, 2013, 10th International Conference on Group IV Photonics.

Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer

Sang-Pil Sim, Joo-Sun Choi, Choong-Ki Kim, 1991 .