J. Albert

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

E. Simoen, R. Ritzenthaler, N. Horiguchi, 2014, 2014 IEEE International Electron Devices Meeting.

Cleaning and Strip Requirement for Metal Gate Based CMOS Integration

T. Schram, S. Kubicek, R. Vos, 2009 .

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

Naoto Horiguchi, Wilfried Vandervorst, Tom Schram, 2014, IEEE Transactions on Electron Devices.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

Vincent Wiaux, David Hellin, Johan Vertommen, 2013, Advanced Lithography.

Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

Naoto Horiguchi, Jerome Mitard, Eddy Simoen, 2016, IEEE Transactions on Electron Devices.