Y. Yu

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

Niraj K. Jha, Ye Yu, N. Jha, 2017, ACM J. Emerg. Technol. Comput. Syst..

Energy-Efficient Monolithic Three-Dimensional On-Chip Memory Architectures

Niraj K. Jha, Ye Yu, N. Jha, 2018, IEEE Transactions on Nanotechnology.

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Niraj K. Jha, Ye Yu, Weifeng Zhang, 2019, IEEE Transactions on Computers.

SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference pdf

Niraj K. Jha, Ye Yu, N. Jha, 2019, IEEE Transactions on Emerging Topics in Computing.

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

Niraj K. Jha, Ye Yu, N. Jha, 2018, IEEE Transactions on Multi-Scale Computing Systems.