Kerim Kalafala

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Chandramouli Visweswariah, Ralph H. J. M. Otten, Jochen A. G. Jess, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

First-Order Incremental Block-Based Statistical Timing Analysis

K. Ravindran, Jeffrey G. Hemmett, Chandramouli Visweswariah, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Microprocessor Designs

Sachin Gupta, Chandu Visweswariah, Debjit Sinha, 2009 .

A distributed timing analysis framework for large designs

Martin D. F. Wong, Tsung-Wei Huang, Natesan Venkateswaran, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Prototype for a large-scale static timing analyzer running on an IBM Blue Gene

Christopher D. Carothers, Kerim Kalafala, Akintayo Holder, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

First-Order Incremental Block-Based Statistical Timing Analysis

Natesan Venkateswaran, Kaushik Ravindran, Kerim Kalafala, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Practical statistical static timing analysis with current source models

Vladimir Zolotov, Debjit Sinha, Michael H. Wood, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Chandramouli Visweswariah, Ralph H. J. M. Otten, Jochen A. G. Jess, 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Survey of SSTA Techniques with Focus on Accuracy and Speed

Sachin S. Sapatnekar, Vladimir Zolotov, Daniel K. Beece, 2017 .