Cheng-Yeh Wang

An effective physical synthesis technique for multiplier

Jing-Yang Jou, Cheng-Yeh Wang, Ya-Chi Yang, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Jing-Yang Jou, Cheng-Yeh Wang, Chih-Chieh Chou, 2005, ASP-DAC.

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

Jieh-Tsorng Wu, Cheng-Yeh Wang, Zwei-Mei Lee, 2007, IEEE J. Solid State Circuits.

Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming

Jing-Yang Jou, Cheng-Yeh Wang, Hsu-Wei Huang, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Hybrid Wordlength Optimization Methods of Pipelined FFT Processors

Jing-Yang Jou, Cheng-Yeh Wang, Chih-Bin Kuo, 2007, IEEE Transactions on Computers.

Hierarchical architecture for network-on-chip platform

Jing-Yang Jou, Lan-Da Van, Cheng-Yeh Wang, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

An efficient heterogeneous tree multiplexer synthesis technique

Jing-Yang Jou, Cheng-Yeh Wang, Hsu-Wei Huang, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

Jieh-Tsorng Wu, Cheng-Yeh Wang, Zwei-Mei Lee, 2006, IEEE Journal of Solid-State Circuits.

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Jing-Yang Jou, Cheng-Yeh Wang, Chih-Chieh Chou, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..