Chang-Kyo Lee

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

Nam Sung Kim, Chang-Kyo Lee, Hyung-Joon Chi, 2021, IEEE Journal of Solid-State Circuits.

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration

Yun-Sik Park, Chang-Kyo Lee, Jung-Bae Lee, 2019, 2019 Symposium on VLSI Circuits.

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Jaehoon Jung, Chang-Kyo Lee, Hyung-Joon Chi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).