Saburo Muroga

发表

Redundancy check technique for designing optimal networks by branch-and-bound method

Hung Chi Lai, Tomoyasu Nakagawa, Saburo Muroga, 2004, International Journal of Computer & Information Sciences.

Design of MOS networks in single-rail input logic for incompletely specified functions

Hung Chi Lai, Saburo Muroga, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Optimal Networks of NOR-OR Gates for Functions of Three Variables

Saburo Muroga, Charles R. Baugh, C. S. Chandersekaran, 1972, IEEE Transactions on Computers.

Two problems on threshold functions

Saburo Muroga, Calvin C. Elgot, 1961, SWCT.

The Parametron Digital Computer MUSASINO-1

Kensuke Takashima, Saburo Muroga, 1959, IRE Trans. Electron. Comput..

The principle of majority decision logical elements and the complexity of their circuits

Saburo Muroga, S. Muroga, 1959, IFIP Congress.

Logic Properties of Transistor Circuits

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Programmable Logic Devices

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Enumeration of Threshold Functions of Eight Variables

Saburo Muroga, Charles R. Baugh, Teiichi Tsuboi, 1970, IEEE Transactions on Computers.

VLSI system design

Saburo Muroga, S. Muroga, 1982 .

Logic Synthesizer with Optimizations in Two Phases

Saburo Muroga, Ko Yoshikawa, S. Muroga, 2000, The VLSI Handbook.

Basic Theory of Logic Functions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Adaptive Linear Classifier by Linear Programming

Toshihide Ibaraki, Saburo Muroga, 1970, IEEE Trans. Syst. Sci. Cybern..

Minimal covering problem and PLA minimization

Saburo Muroga, Ming Huei Young, 2004, International Journal of Computer & Information Sciences.

Gate arrays

Saburo Muroga, S. Muroga, 2000 .

Sequential networks

Saburo Muroga, S. Muroga, 2000 .

Parallel Binary Adders with a Minimum Number of Connections

Saburo Muroga, Akito Sakurai, 1983, IEEE Transactions on Computers.

Binary Decision Diagrams

Saburo Muroga, Shin-ichi Minato, S. Muroga, 2000, The VLSI Handbook.

Timing optimization for multi-level combinational networks

Saburo Muroga, Kuang-Chien Chen, S. Muroga, 1990, DAC '90.

Logic optimization of MOS networks

Saburo Muroga, Johnson Chan Limqueco, 1991, 28th ACM/IEEE Design Automation Conference.

Generation and Asymmetry of Self-Dual Threshold Functions

Saburo Muroga, 1965, IEEE Trans. Electron. Comput..

Optimization methods for lookup-table-based FPGAs using transduction method

Yahiko Kambayashi, Saburo Muroga, Shigeru Yamashita, 1995, ASP-DAC '95.

Minimum Parallel Binary Adders with NOR (NAND) Gates

Hung Chi Lai, Saburo Muroga, S. Muroga, 1979, IEEE Transactions on Computers.

Logical Design of Optimal Digital Networks by Integer Programming

Saburo Muroga, 1970 .

Design of Optimal Switching Networks by Integer Programming

Toshihide Ibaraki, Saburo Muroga, 1972, IEEE Transactions on Computers.

Ultra Large-Scale Integration Design

Saburo Muroga, S. Muroga, 2003 .

Lower Bound of the Number of Threshold Functions

Saburo Muroga, Iwao Toda, 1966, IEEE Trans. Electron. Comput..

Absolute Minimization of Completely Specified Switching Functions

Saburo Muroga, Sung Je Hong, S. Muroga, 1991, IEEE Trans. Computers.

The Transduction Method-Design of Logic Networks Based on Permissible Functions

Yahiko Kambayashi, Hung Chi Lai, Saburo Muroga, 1989, IEEE Trans. Computers.

Comparisons of different design approaches

Saburo Muroga, 2000 .

Logic Synthesizer by the Transduction Method

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight

Saburo Muroga, 1962, SWCT.

Pass Transistors

Saburo Muroga, Kazuo Yano, S. Muroga, 2000, The VLSI Handbook.

Lower Bounds of the Number of Threshold Functions and a Maximum Weight

Saburo Muroga, S. Muroga, 1962, IEEE Trans. Electron. Comput..

Optimization methods for look-up table-type FPGAs based on permissible functions

Yahiko Kambayashi, Saburo Muroga, Shigeru Yamashita, 1996, Systems and Computers in Japan.

Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks

Toshihide Ibaraki, Saburo Muroga, Charles R. Baugh, 1971, Oper. Res..

Logic Synthesis with AND and OR Gates in Multi-levels

Saburo Muroga, Yuichi Nakamura, S. Muroga, 2000, The VLSI Handbook.

Full-Custom and Semi-Custom Design

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

SYLON-REDUCE: an MOS network optimization algorithms using permissible functions

Saburo Muroga, Johnson Chan Limqueco, 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Logic Synthesis with NAND (or NOR) Gates in Multi-levels

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Simplification of Logic Expressions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Properties of Wired Logic

Yahiko Kambayashi, Saburo Muroga, S. Muroga, 1986, IEEE Transactions on Computers.

Parallel multipliers with NOR gates based on G-minimum adders

Saburo Muroga, Ging-Shung Yu, 2004, International Journal of Computer & Information Sciences.

SYLON-DREAM: a multi-level network synthesizer

Saburo Muroga, Kuang-Chien Chen, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Expressions of Logic Functions

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Design of logic circuits with wired-logic utilizing transduction method

Yahiko Kambayashi, Saburo Muroga, Shigeru Yamashita, 1996, Systems and Computers in Japan.

Emitter-Coupled Logic

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables

Saburo Muroga, Ming Huei Young, 1985, IEEE Transactions on Computers.

On the capacity of a noisy continuous channel

Saburo Muroga, S. Muroga, 1957, IRE Trans. Inf. Theory.

Input assignment algorithm for decoded-PLAs with multi-input decoders

Saburo Muroga, Kuang-Chien Chen, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions

Tomoyasu Nakagawa, Saburo Muroga, Ming Huei Young, 1979, IEEE Transactions on Computers.

Logic Synthesis AND and OR Gates in Two Levels

Saburo Muroga, S. Muroga, 2003 .

Minimization of Logic Networks Under a Generalized Cost Function

Hung Chi Lai, Saburo Muroga, S. Muroga, 1976, IEEE Transactions on Computers.

Cell-Library Design Approach

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Optimal One-Bit Full Adders With Different Types of Gates

Saburo Muroga, Tso-Kai Liu, Keith R. Hohulin, 1974, IEEE Transactions on Computers.

Logic Networks of Carry-Save Adders

Hung Chi Lai, Saburo Muroga, 1982, IEEE Trans. Computers.

Field-Programmable Gate Arrays

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions"

Saburo Muroga, Robert Brian Cutler, 1979, IEEE Trans. Computers.

Functional forms of majority functions and a necessary and sufficient condition for their realizability

Saburo Muroga, S. Muroga, 1961, SWCT.

Logic design and switching theory

Saburo Muroga, S. Muroga, 1979 .

Sequential Networks with AND and OR Gates

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

Logic Synthesis with a Minimum Number of Negative Gates

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Logic Synthesis with AND and OR Gates in Two Levels

Saburo Muroga, S. Muroga, 2000, The VLSI Handbook.

Useless prime implicants of incompletely specified multiple-output switching functions

Saburo Muroga, Robert Brian Cutler, 2004, International Journal of Computer & Information Sciences.

A resynthesis approach for network optimization

Masahiro Fujita, Yusuke Matsunaga, Saburo Muroga, 1991, 28th ACM/IEEE Design Automation Conference.

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables

Hung Chi Lai, Saburo Muroga, S. Muroga, 1987, IEEE Transactions on Computers.

Computer-Aided Logic Synthesis for VLSI Chips

Saburo Muroga, S. Muroga, 1991, Adv. Comput..

Binary Decision Diagrams

Saburo Muroga, Shi-ichi Minato, S. Muroga, 2000, The VLSI Handbook.

Threshold logic and its applications

Saburo Muroga, S. Muroga, 1971 .

Logic Synthesizers, The Transduction Method and Its Extension, Sylon

Saburo Muroga, 1993 .

Mask-Programmable Gate Arrays

Saburo Muroga, S. Muroga, 1999, The VLSI Handbook.

An implicit enumeration program for zero-one integer programming

Toshihide Ibaraki, Saburo Muroga, Charles R. Baugh, 2005, International Journal of Computer & Information Sciences.

Derivation of Minimal Sums for Completely Specified Functions

Saburo Muroga, Robert Brian Cutler, 1987, IEEE Transactions on Computers.

On the Capacity of a Discrete Channel, II. Mathematical Expression of the Capacity of a Noisy Channel which is Expressible by Corresponding Two Multi-state Diagrams

Saburo Muroga, 1956 .

Functional forms of dual-comparable functions and a necessary and sufficient condition for readability of a majority function

Saburo Muroga, 1964, IEEE Transactions on Communication and Electronics.

Automated Logic Design of Mos Networks

Hung Chi Lai, Saburo Muroga, S. Muroga, 1985 .